Why a Reed-Solomon Forward Correction Error in the Ethernet PHY can help limit area and power.
The increase in bandwidth is driving more innovations in the Ethernet physical layer technology to combat numerous challenges like channel loss, inter-symbol interference and more importantly error detection and correction. It is imperative to have a mechanism in place to detect and correct errors as data is transmitted and received, while maintaining small silicon area and low power consumption. One technique is the forward error correction (FEC), which detects burst errors and corrects them at the receiver without the need for data retransmission, which is costly and adds to inefficiencies and latency. FEC is based on error-correcting codes written by Reed-Solomon and is now known as Reed-Solomon Forward Error Correction (RS-FEC). The IEEE 802.3 standard has since defined different RS-FEC modes supporting today’s 25Gbps Ethernet and the evolving 50Gbps Ethernet speeds.
This paper explains how a common Reed-Solomon Forward Error Correction implementation in the Ethernet physical layer can help SoC designers keep silicon footprint small and power consumption low, even at high-speeds beyond 10Gbps. To read more, click here.
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