Author's Latest Posts


Exploiting The Java Deserialization Vulnerability


In the security industry, we know that operating on untrusted inputs is a significant area of risk; and for penetration testers and attackers, a frequent source of high-impact issues. Serialization is no exception to this rule, and attacks against serialization schemes are innumerable. Unfortunately, developers enticed by the efficiency and ease of reflection-based and native serialization cont... » read more

Establish A Software Procurement Process To Manage Supply Chain Risk


Improving the procurement language in your software contracts is an effective way to convey requirements for built-in security. Too many examples of afterthought bolt-on security have put enterprises and users at risk due to exploitable software. Historically, there has been no shared liability associated with software because standard contracts have absolved software suppliers and outsource... » read more

The Basics Of Foundation IP For Automotive ICs


This white paper provides a broad overview of requirements that must be considered in order to design and manufacture integrated circuits (ICs) for the automotive sector. The paper looks specifically at the standards that apply to Foundation IP - logic libraries, embedded memories, and memory built-in self-test (BIST) - for different automotive IC functions and how reliability grades affect IP ... » read more

ARC HS4x And HS4xD CPUs


Synopsys’ DesignWare ARC CPUs comprise a family of highly configurable and customizable processor cores, which ship in nearly two billion chips per year. ARC’s popularity in embedded devices makes the company second only to ARM in the number of chips that integrate its licensable CPUs. More than 230 ARC licensees use the cores in products that span a broad range of embedded applications, su... » read more

Saving Power In A UFS Implementation Leveraging MIPI M-PHY And UniPro


The JEDEC Universal Flash Storage (UFS) has become the mobile storage standard of choice for today’s high-end smartphones and tablets mainly due to the specification’s performance and power advantages over other existing solutions. These advantages become critical to meet end users’ requirements for higher responsiveness and increased capabilities. For example, end users expect to transmi... » read more

Avoiding The Top 10 Software Security Design Flaws


Half of the software-related security defects that provide entry to threat agents are not found in buggy code – they are flaws embedded in software design. The IEEE Center for Secure Design brought together some of the foremost experts in software security in a working group to tackle the issue of secure software design. This whitepaper covers their findings. Find out why so many design... » read more

Shift Left Your FPGA Design For Faster Time To Market


In just a few short years, FPGAs have become an integral part of system design for many applications either as a co-processor or the main system processor. As FPGA size and performance increases, system designers are able to utilize them for more tasks. The increased size and performance translates to greater complexity, which is further compounded as designers try to integrate more functionali... » read more

IC Validator Programmable EERC Mixed Mode Checking Technology


Traditional visual inspection or manual checking for electrical rule compliance is both time consuming and error prone. A new, comprehensive reliability solution is needed to reduce time to market, improve reliability and ensure longer device operation. This paper is a companion to the introductory IC Validator programmable Extended Electrical Rule Check (EERC) white paper on netlist domain che... » read more

Building Secure Software At Enterprise Scale


The cost of finding and remediating a software defect reduces dramatically the earlier it is found in the development life cycle. This is not new news. What is new news is an approach that builds security into the development process in a way that is easy for developers to adopt, without slowing down their workflow. Download the paper to learn how you can: Prevent common bugs and flaw... » read more

VCS Fine-Grained Parallelism Simulation Performance Technology


Learn how fine-grained parallelism simulation technology enables delivery of breakthrough parallel simulation performance improvement needed to reduce turn-around time for critical-path tests. » read more

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