Author's Latest Posts

Reliable Automotive IC Design With Galaxy Design Platform
By Synopsys - 25 May, 2016 - Comments: 0

Automakers are continuously integrating new advanced driver assistance systems and in-vehicle infotainment (IVI) technologies to provide drivers and their passengers with improved safety, navigation, entertainment and communications. Cars are becoming safer and more efficient as they are increasingly capable of sensing and responding to their on-road environment. These trends present additional... » read more

Achieve Functional Safety And High Uptime Using TMR
By Synopsys - 11 May, 2016 - Comments: 0

A look at how to build reliable FPGA-based designs, employing triple modular redundancy. To read more, click here. » read more

Securing The Internet of Things Using Hardware Rooted Processor Security — An Architect’s Guide
By Synopsys - 27 Apr, 2016 - Comments: 0

Security is a key requirement for Internet of Things (IoT) devices and must be considered for all aspects of the design. This paper provides an overview of security basics, feature requirements, technical solutions, and associated system-level trade-offs for implementing security in IoT devices. Making the required trade-offs is significantly easier by leveraging secure, proven building blocks ... » read more

Foundation IP For 7nm FinFETs: Design And Implementation
By Synopsys - 13 Apr, 2016 - Comments: 0

Learn about the challenges of IP design and implementation for 7nm FinFETs. Along with the performance and area benefits that the node brings, designers must understand the significant technical challenges stemming from increasing variability associated with tighter pitches and more complex lithography steps. Design for variability and reliability considerations will require comprehensive model... » read more

Optimizing DDR Memory Subsystem Efficiency
By Synopsys - 23 Mar, 2016 - Comments: 0

This whitepaper applies virtual prototyping tools and best practice techniques to optimize the DDR memory subsystem configuration for a specific SoC application. Starting from a hypothetical Mobile Application Processor design, we will illustrate step-by step how to optimize: Address mapping Clock frequency Quality of Service (QoS) To read more, click here. » read more

Addressing Three Critical Challenges Of USB Type-C Implementation
By Synopsys - 09 Mar, 2016 - Comments: 0

As designers are create new products and system-on-chips (SoCs) with USB Type-C support, they need to be aware of datapath and hardware/software partitioning challenges. The SoC and system design must be partitioned to support the specification’s requirements for precision analog circuitry plus high voltage/high current switches, and Type-C management software must be partitioned to execute o... » read more

Optimizing DDR Memory Subsystem Efficiency
By Synopsys - 24 Feb, 2016 - Comments: 0

The memory subsystem sits at the core of a System-on-Chip (SoC) platform and can make all the difference between a well-designed system meeting its performance requirements and a system that delivers poor performance, or even fails to operate correctly. State-of-the-art DDR memory controllers use advanced arbitration and scheduling policies to optimize DDR memory efficiency. At the same time, t... » read more

Optimizing LPDDR4 Performance And Power With Multi-Channel Architectures
By Synopsys - 10 Feb, 2016 - Comments: 0

PDDR4 offers huge bandwidth in a physically small PCB area and volume; up to 25.6 GByte/s of bandwidth at a 3,200 Mbps data rate from a single 15mmx15mm LPDDR4 package when two dies are packaged together. LPDDR4 builds on the success of LPDDR2 and LPDDR3 by adding new features and introducing a major architectural change. This white paper explains how LPDDR4 is different from all previous JEDEC... » read more

IC Compiler II Multi-Level Physical Hierarchy Floorplanning
By Synopsys - 27 Jan, 2016 - Comments: 0

Large, complex SoC designs require hierarchical layout methodologies that span multiple levels of physical hierarchy. Many EDA tools only handle two levels of physical hierarchy at a given time resulting in longer layout schedules that are risky at best. Synopsys' IC Compiler II provides automation designs with multiple levels of hierarchy that minimizes time to results, provides best QoR, and ... » read more

True Random Number Generators For Truly Secure Systems
By Synopsys - 13 Jan, 2016 - Comments: 0

Random numbers form the basis, or root, of most security systems. Yet the methods for generating random numbers vary widely in practice as well as efficacy. Over time, many popular randomization algorithms and circuit implementations have been shown to be provably flawed. The paper will examine current methods for generating random numbers based on various sources of entropy as well as their as... » read more

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