MoS2 Memristors With Fast Switching Speed and Low Power Consumption (AMO, RWTH Aachen et al.)


A new technical paper titled "Intermediate Resistive State in Wafer-Scale Vertical MoS2 Memristors Through Lateral Silver Filament Growth for Artificial Synapse Applications" was published by researchers at AMO GmbH, RWTH Aachen, Forschungszentrum Jülich, Peter Grünberg Institute, Eindhoven University of Technology et al. Abstract "Memristors based on 2D materials have garnered signifi... » read more

Chip Industry Technical Paper Roundup: Dec 30


New technical papers recently added to Semiconductor Engineering’s library: [table id=509 /] Find more semiconductor research papers here. » read more

Chip Industry’s Top Videos 2025


Rising complexity, new architectures, and AI's permeation of nearly everything left engineers struggling to keep up in 2025, as evidenced by this year's viewership numbers. Among the hottest topics were verification, agentic AI, DRAM/HBM, optimization of data movement, chiplets, and heterogeneous integration, but there was steady traffic growth across all sectors. Top 10 most-watched videos ... » read more

Chip Industry Week In Review


Deals: NVIDIA inked a $20B non-exclusive licensing deal with Groq for its inference technology. The startup's founder, Jonathan Ross, and some other employees will join NVIDIA to assist in scaling and advancing the technology. The non-exclusive licensing deal, versus an outright purchase, is a tool other companies have used to avoid antitrust regulation. Samsung Ventures made a strategic inv... » read more

The Impact Of DRAM Writes On DDR5-Based Systems (Georgia Tech)


A new technical paper titled "BARD: Reducing Write Latency of DDR5 Memory by Exploiting Bank-Parallelism" was published by Georgia Tech. Abstract "This paper studies the impact of DRAM writes on DDR5-based system. To efficiently perform DRAM writes, modern systems buffer write requests and try to complete multiple write operations whenever the DRAM mode is switched from read to write. Whe... » read more

Reliability And Traceability In Advanced Packages


The move from planar SoCs to advanced packages can improve performance and provide flexibility in large designs, which are difficult to fit onto a single reticle-sized die. But ensuring the device works as expected remains a challenge. There are multiple packaging options to choose from — 2.5D, fan-out wafer-level packaging, 3D-ICs, and various types of system-in-package — and many possible... » read more

Blog Review: Dec. 24


Cadence's Jakob Engblom shares highlights from the recent SDV Europe conference, including why software-defined vehicles will require much closer, faster collaboration between suppliers and customers, with virtualization for software development and testing taking on a key role, as well as API questions and tire sensors. Synopsys' Tom De Schutter and Marc Serughetti predict that new cars wil... » read more

AFM-Based Protocol for Characterizing the Incipient Stages of Plasticity on Hybrid Bonding-Ready Copper Pads (NIST, Intel, Colorado School of Mines)


A new technical paper titled "Probing the Nanoscale Onset of Plasticity in Electroplated Copper for Hybrid Bonding Structures via Multimodal Atomic Force Microscopy" was published by researchers at the National Institute of Standards and Technology, Intel, and Colorado School of Mines. Excerpt  "The slowdown of Moore’s law has elicited a paradigm shift whereby shrinking of in-plane dim... » read more

Nano Gap MEMS Switches for Power Gating in Low Power Systems (KAIST, Chonnam National Univ.)


A new technical paper titled "Ultra-Fast, Low-Resistance Nano Gap Electromechanical Switch for Power Gating Applications" was published by researchers at KAIST and Chonnam National University. Abstract "The growing demand for artificial intelligence and high-performance computing accelerates concerns over leakage power in highly integrated semiconductor systems. Power gating can reduce th... » read more

Economic And Scalable Algorithm-Driven On-Chip Integration Approach (USC)


A new technical paper titled "Algorithm-Driven On-Chip Integration for High Density and Low Cost" was published by researchers at University of Southern California. Abstract "Growing interest in semiconductor workforce development has generated demand for platforms capable of supporting large numbers of independent hardware designs for research and training without imposing high per-proje... » read more

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