Macro Defect Inspection For Mission-Critical Defense, Aerospace, And Advanced R&D Fabs

By Errol Akomer - 18 Dec, 2025 - Comments: 0

Some fabs build consumer chips that sit inside phones and laptops. Others build chips that must survive in orbit, under the Arctic ice, or deep beneath the Earth’s surface. Fabs serving defense, aerospace, national laboratories, and other advanced R&D programs operate under some of the most stringent requirements in the industry. For these facilities, yield is not the only concern. Sec... » read more

Benefits And Limits Of Using ML For Materials Discovery

By Katherine Derbyshire - 18 Dec, 2025 - Comments: 0

Machine learning tools can accelerate all stages of materials discovery, from initial screening to process development. Whether the goal is to identify new applications for known materials or to design new molecules for a particular task, these tools help materials scientists find correlations in large data libraries. Still, machine learning tools are not magic. “Software tools are only as... » read more

Advanced Packaging: Driving Innovation, Performance, And New System Capabilities

By Cassandra Melvin - 18 Dec, 2025 - Comments: 0

Advanced packaging is no longer operating behind the scenes. The technology of advanced packaging is helping to sustain the speed of the semiconductor industry’s improvement in power and performance, even as the Moore’s Law roadmap for wafer-level scaling comes under strain. At the Advanced Packaging Conference during SEMICON Europa 2025 in Munich, global experts examined the growth tr... » read more

Analysis of EM Side Channel Attacks On Smartphones (Fraunhofer AISEC, BSI, TUM)

By Technical Paper Link - 17 Dec, 2025 - Comments: 0

A new technical paper titled "Breaking ECDSA with Electromagnetic Side-Channel Attacks: Challenges and Practicality on Modern Smartphones" was published by researchers at Fraunhofer Institute for Applied and Integrated Security (AISEC), German Federal Office for Information Security, and TU Munich. Abstract "Smartphones handle sensitive tasks such as messaging and payment and may soon sup... » read more

Reducing The Expertise Required For Software Developers To Participate In Chip Creation (USC)

By Technical Paper Link - 17 Dec, 2025 - Comments: 0

A new technical paper titled "A Vertically Integrated Framework for Templatized Chip Design" was published by researchers at University of Southern California. Abstract "Developers who primarily engage with software often struggle to incorporate custom hardware into their applications, even though specialized silicon can provide substantial benefits to machine learning and AI, as well as ... » read more

A Scalable and Cost-Effective Approach to Fabricate Memristors for ReRAMs and Neuromorphic Computing (U. of Pisa, U. of Pavia et al.)

By Technical Paper Link - 17 Dec, 2025 - Comments: 0

A new technical paper titled "Fast prototyping of memristors for ReRAMs and neuromorphic computing" was published by researchers at Università di Pisa, Università di Pavia, Quantavis s.r.l., and the Instituto de Ciencia de Materiales de Madrid. Abstract "The growing demand for energy-efficient computing in artificial intelligence requires novel memory technologies capable of storing and... » read more

Scalable End-To-End Test Solutions For Today’s Complex SoCs

By Srikanth Venkat Raman - 17 Dec, 2025 - Comments: 0

By Srikanth Venkat Raman and Sri Ganta Today’s highly complex and large system on chip (SoC) devices and systems present many challenges to be addressed from manufacturing tests to the field while meeting stringent requirements for test costs, test quality, yield, debug, and turn-around-times. Scalable and efficient end-to-end test solutions that scale to large and complex SoC design cores... » read more

AI Workloads at the Edge: Ensuring Performance, Privacy, and Security

By Ann Mutschler - 17 Dec, 2025 - Comments: 0

Experts At The Table: Semiconductor Engineering gathered a group of experts to discuss why some AI workloads are better suited for on-device processing to achieve consistent performance, avoid network connectivity issues, reduce cloud computing costs, and ensure privacy. The panel included Frank Ferro, group director in the Silicon Solutions Group at Cadence; Eduardo Montanez, vice president a... » read more

Blog Review: Dec. 17

By Jesse Allen - 17 Dec, 2025 - Comments: 1

Cadence's Shyam Sharma checks out what's new in the latest Open NAND Flash Interface 5.2 standard, including a Separate Command Address protocol that allows Hosts to optimize the command and data scheduling to increase overall available bandwidth. Siemens' Kyle Fraunfelter and Melville Bryant contend that improving semiconductor manufacturing and fab sustainability starts with a digital twin... » read more

Research Bits: Dec. 16

By Jesse Allen - 16 Dec, 2025 - Comments: 0

Back-end integration Researchers from Massachusetts Institute of Technology (MIT) and the University of Waterloo propose a back-end integration platform that enables the fabrication of transistors and memory devices in a single compact stack on a chip. The approach uses amorphous indium oxide as the active channel layer of the back-end transistor. The properties of indium oxide allow a thin... » read more

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