Week In Review: Manufacturing, Test
6nm vs 5nm processes; Intel exits 5G chip biz; deep learning.
Week in Review: IoT, Security, Auto
Drone inspections; war exclusion; Apple’s LiDAR; IPOs.
Week In Review: Design, Low Power
Intel buys Omnitek; Qualcomm, Apple drop litigation; 112G Long Reach SerDes; EDA & IP down in Q4.
The Precision Knob
From design through manufacturing, accuracy is becoming a differentiator.
More Rare Earth Rumblings
Events in China and elsewhere are impacting the market for rare earths.
What’s in a Name?
Test Vision 2020 may need a new moniker.
NIWeek Test Talk
National Instruments executives discuss semiconductor testing.
The Best in Test
VLSI Research recognizes leading test vendors.
Looking For The Elephant In The Valley
Female role models doing exceptional things in tech have always existed. Hope...
The Week in Review: IoT
IoT market growth; investments in IoT; Cambium products.
Generically Reusable IP No One Uses
If we just keep putting generically reusable on the box, all we’re doing is...
More Memory And Processor Tradeoffs
Why power, performance and area are becoming increasingly difficult to balance.
The Weather Report: 2018 Study On IC/ASIC Verification Trends
Increased design size is only one dimension of the growing complexity challenge.
GDDR6 And HBM2: Signal Integrity Challenges For AI
Why memory choices for AI systems depend on the application.
The Precision Knob
From design through manufacturing, accuracy is becoming a differentiator.
More Rare Earth Rumblings
Events in China and elsewhere are impacting the market for rare earths.
New Plastics Can Speed Flexible Printed Electronics Development
New polymer substrates offer printed electronics exciting capabilities.
Preparing For War On The Edge
The tech world is planning for an onslaught of data, but it's far from clear ...
How To Manage DFT For AI Chips
AI-specific processors call for design-for-test techniques that boost time-to...
How Do I Know? A Machine Told Me So
Emerging machine learning techniques are pushing the boundaries of what compu...
The 7nm Pileup
Why are so many companies rushing to do 7nm designs?
Mine Cryptocurrencies Sooner, Part 2
What lessons have newer cryptocurrencies learned from Bitcoin that make them ...
Auto Reliability At The System Level
Why different starting points and definitions could have a big impact on auto...
The Value Of A Model
How much would you pay for a model? Recently, the answer to that has been $$$.
Fibonacci And Honey Bees Have Something In Common: A Sweet Spot For Formal
Can assertions enable engineers to design IP that is correct by construction?
What Just Happened?
In the period of a year the semiconductor industry has transformed into somet...
Crunch Time
The network as we've known it for a couple of generations is changing before ...
The “Last Simple Node” And the Internet of Things
A huge amount of foundry space built in the last five years will be converted...
Virtual Packages Improve Signal Integrity
How to optimize chiplet architectures, including reducing in-package loss and...
SerDes For Chiplets
The key goals are low power and high bandwidth over extremely short distances.
How Much Data Can Be Pushed Through Copper Wires?
Pushing toward the Shannon signaling capacity using less energy consumption.
Crossing The Chasm: Uniting SoC And Package Verification
EDA companies, OSATs, and foundries must collaborate to ensure wafer-level pa...
Will EUV Kill Multi-Patterning?
Even with EUV in play, i193 multi-patterning may still be the most cost effec...
Extra! Extra! Read All About It!
ASML is going into the pellicle business!
Visiting The Future At CLEO
Pointing light in different directions: mid-infrared microscopy, quantum cryp...
Advanced Lithography: Moore’s Law Moves On
If designers can stand all the rules that come with quadruple patterning, the...
Five steps to successful threat modeling
How to build a security plan and put it into action.
Reducing Time To Market For Security Solutions
Complex regulatory requirements and the time it takes to make security soluti...
Published on November 1st, 2018 by
Udi Maor
When The IoT Really Works
A look at the necessary ingredients to transform businesses.
Samsung Foundry’s Business Strategy
A look at manufacturing changes and advanced technology updates.
Does IoT Change Design?
Is the Internet of Things really something that will impact system design, or...
EDA Resurgence Through Open Flows
The EDA industry can experience a resurgence if truly open interfaces and ope...
The Perilous Path From Technology To Product
Just because a product can do more doesn’t mean it should—or that you’l...
3D Construction Ahead
Building sub-wavelength structures using photons, and using 3D printers to cr...
ReRAM Gains Even More Steam
Latest manufacturing techniques are being explored as commercial products beg...
Molecular Imprints becomes a virtual reality company
Remainder of company acquired by Magic Leap, a VC-funded startup led by Google.
Siemens To Buy Mentor For $4.5B
Updated: Deal adds mechanical, thermal, electrical and embedded software capa...
Samsung To Buy Harman For $8B
Tier 1 acquisition boosts automotive portfolio.
Qualcomm + NXP = IoT Powerhouse
What the Qualcomm-NXP deal means for IoT.
Week in Review: IoT, Security, Auto
Drone inspections; war exclusion; Apple’s LiDAR; IPOs.
Week in Review: IoT, Security, Auto
Smarter buildings; 5G security; Tesla news.
Major Growth For Knowledge Center
An update on the Knowledge Center, plus a few pop quizzes.
Industry Collaboration Starts
Check out all the new stuff...And this is just the beginning.
Welcome To The Knowledge Center
There are more than 1,600 information pages already in the system, and many m...
Semicon West Lithography Report
OK, so I didn't go to Semicon West. That doesn't mean I don't have opinions ...
SPIE Advanced Lithography 2013 – day 2
There were some great papers at AL on Tuesday. Here are some of my favorite...
SPIE Advanced Lithography 2013 – day 4
The last day of the conference gave the tool updates. So how is EUV progress...
Designing For The Edge
Growth in data is fueling many more options, but so far it's not clear which ...
Power/Performance Bits: April 16
Faster CNN training; efficient flash for data centers; static negative capaci...
The Weather Report: 2018 Study On IC/ASIC Verification Trends
Increased design size is only one dimension of the growing complexity challenge.
Getting Ready For The IoT
Preparing for the next seismic shift in the semiconductor industry.
Metrics For Measuring Performance And Power In IoT SoC Designs
Benchmarking can provide relevant data for real-world applications.
The Real Value In Customizing Instructions
How to enable an order of magnitude in power savings for IoT applications.
Week In Review: Manufacturing, Test
6nm vs 5nm processes; Intel exits 5G chip biz; deep learning.
The Precision Knob
From design through manufacturing, accuracy is becoming a differentiator.
More Rare Earth Rumblings
Events in China and elsewhere are impacting the market for rare earths.
Week In Review: Manufacturing, Test
6nm vs 5nm processes; Intel exits 5G chip biz; deep learning.
Week in Review: IoT, Security, Auto
Drone inspections; war exclusion; Apple’s LiDAR; IPOs.
Week In Review: Design, Low Power
Intel buys Omnitek; Qualcomm, Apple drop litigation; 112G Long Reach SerDes; ...
Apple Vs. FBI, Take Two
No system can ever be fully secured.
Oh, The Hypocrisy
Did Apple really claim it's protecting the privacy of iPhone customers?
IoE Things Are Spying On Us
Direct marketers are using hiddenware to figure out what we're thinking.
ARM Buys Carbon
Deal allows ARM to create virtual prototypes for performance and power analys...
Customized On-Chip Process Monitors
Using ring oscillators to validate design signoff methodology and silicon pro...
Inside The Hybrid Memory Cube
A look at how to break through the memory bandwidth wall.
TSMC: 10nm To Be Greater Than 10% Of 2017 Wafer Revenue
10nm heads into full swing, with 7nm and 5nm on the horizon.
Green Computing: GPUs Strike Back
Speed matters, but so does efficiency.
Making Waves In Deep Learning
How deep learning applications will map onto a chip.
A Strategy For Designing For Power With FinFETs
Moving from 28nm to finFETs provides a 1.2X improvement in power and performa...
Doing More With RTL Power Analysis: Smart Synthesis Architecture
The migration to finFET processes requires a serious focus on dynamic power c...
Microarchitecture Design For Low Power
A look at first-in, first-out design tradeoffs.
The Economics Of Moore’s Law
Ten years from now, CMOS will seem as old-fashioned as vacuum tubes.
Published on February 18th, 2016 by
Imec
The Internet Of Power Also Benefits From Moore’s Law
It's increasingly possible to stack technologies to produce smart systems.
Published on January 21st, 2016 by
Imec
Betting On Wright’s Law
Moore’s Law is primarily an economic law, but it can be expanded and applie...
Published on December 17th, 2015 by
Imec
Getting A Handle On RTL X-Verification Challenges
Optimistic simulation behavior can hide bugs in your design that don't show u...
Design And Verification Survey Results
New Poll: Lint topped the list on verification technologies to adopt, followe...
Billion-Gate Signoff
A recommended sign off activity list mean fewer re-spins and a design that is...
Manufacturing Bits: April 16
Water that won’t freeze; modeling water behavior.
System Bits: April 16
Borophene; trapping oxygen; sensitive measurements.
Power/Performance Bits: April 16
Faster CNN training; efficient flash for data centers; static negative capaci...
Moore’s Law Now Requires Advanced Packaging
Experts at the Table, part 1: Shrinking features isn't enough anymore. The bi...
The Role Of EDA In AI
Experts at the Table, part 3: Which aspects of AI implementation should EDA c...
The Automation Of AI
Experts at the Table, part 1: Will the separation of hardware and software fo...
Brave New World Of Mobility
The ITS World Congress in Bordeaux demonstrates the potential of future mobil...
How To Prevent Identity Theft
The number of choices for securing identities is on the rise, but so is the n...
The Promise Of NFC For Industry 4.0
The manufacturing sector has become increasingly digital, which means it can ...
Get Ready For DVCon Europe
New conference will address complex system-level design, mixed signal verific...
2014 Accellera Standards Are Built on Powerful Shoulders
What to watch out for in standards this year and how those changes will affec...
Community, Collaboration And Standards
Where to find standards downloads for the electronics industry and what they'...
Single Vs. Multi-Patterning EUV
Why this choice isn't as obvious as it might look.
Shedding Pounds In Automotive Electronics
Weight is suddenly a major concern for carmakers, but slimming down has reper...
How To Build An Automotive Chip
Changing standards, stringent requirements and a mix of expertise make this a...
Important Changes Ahead
DesignCon panels will focus on system-level power modeling and silicon photon...
See The Internet Of Things…In 3D
The need to integrate a wide variety of functionality economically can't be a...
Multi-Die Packaging Gains Steam
Commercial progress to be unveiled at Global Interposer Technology workshop.
Published on October 6th, 2014 by
Si2
Rogue Valley Microdevices: MEMS Foundry
Oregon-based specialty fab takes different approach.
January’19 Startup Funding: $100M+ Rounds Abound
Billion-dollar funding rounds become more common.
Week In Review: Design, Low Power
Intel buys Omnitek; Qualcomm, Apple drop litigation; 112G Long Reach SerDes; ...
The Role Of EDA In AI
Experts at the Table, part 3: Which aspects of AI implementation should EDA c...
Blog Review: April 17
Embedded power management; Industry 4.0 and semi; security survey.
Machine Learning Based Prediction: Health Behavior on BP
ML algorithm + individual data = personalized recommendations to reduce blood...
Silicon CMOS Architecture For A Spin-based Quantum Computer
UNSW researchers have shown how a quantum computer can be manufactured using ...
Preparing For War On The Edge
The tech world is planning for an onslaught of data, but it's far from clear ...
Racing To The Edge
The opportunity is daunting, but so are the challenges for making all the pie...
New Approaches To Security
Data analytics, traffic patterns and restrictive policies emerge as ways to e...
2017: A Good Year for ATE
Test equipment sales were up, and so were the share prices of ATE stocks.
That Was The Year That Was In Test
2017 featured a big proposed acquisition.
2017 ITC Wrap-up
News from Advantest, Optimal+, Astronics Test Systems.
SoC Connectivity Verification Nightmare
Static checks supplement simulation-based verification.
Physical Lint: Physical Quality Metrics For Your RTL
Improving the quality of RTL leads to more predictable design convergence and...
Taming Lint With Formal
Linting tools take advantage of fast and shallow analysis to provide quick fe...
Commercializing Technology
Once you develop the product, you have to be prepared to sell it.
A Tough Balancing Act
Should you focus on technology or customers?
Moving From Engineering To Management Or Staying On The Technical Track
The stigma of sticking to your technology roots is gone. So what's your next ...
Three Common SoC Power Management Myths
Approaching power management from the architectural design level.
NoC Versus PIN: Size Matters
Complexity and flexibility are the real drivers of fabric choice, not the num...
CSR In Semis
Giving back to the industry is a good thing—and something everyone should b...
Stacking The Deck
Enabling 2.5D and 3D architecture and the supply chain.
Stacking The Deck
Enabling 2.5D and 3D architecture and the supply chain.
Lithography Options For Next-Gen Devices
EUV is the clear winner down to 5nm, but what comes after that may be a combi...
Inspecting IC Packages Using Die Sorters
Why this obscure tool is becoming crucial for finding cracking defects in opt...
Moore’s Law Now Requires Advanced Packaging
Experts at the Table, part 1: Shrinking features isn't enough anymore. The bi...
It’s All In the Sequence
Whether dealing with SoCs or a disaster in space, determining the correct set...
Making Way For Register Specification Software
While more registers means more functionality and configurability, more is no...
The Ultimate Shift Left
Important observations from Einstein and New England's ice traders.
Manufacturing Bits: Dec. 18
Gallium oxide breakthroughs; super-junction SiC; groovy MOSFETs.
Cost Analysis of a Wet Etch TSV Reveal Process
How to scale through-silicon vias and improve industry adoption.
Published on December 10th, 2018 by
Veeco
Multi-Physics At 5/3nm
Why process, voltage and temperature are so interrelated at future nodes, and...
GDDR6 – HBM2 Tradeoffs
What type of DRAM works best where.
Safety Critical Design In Automotive
Finding faults at the chip and system level.
A Semiconductor Approach To Desalination
A new growth market for a very good cause.
Quality And Safety In Automotive Electronics: Venturing beyond ISO-26262
For the automotive market, chips need to last a lot longer than they do in a ...
Power Shifts In Digital Chip Space
The front runner is Intel, and it’s uncertain if or when anyone will catch up.
Improved Efficiency
What’s ahead in power management techniques and why changes are needed.
Near-Threshold Computing
Operating near the level when transistors switch on an off can save lots of p...
ALD Tungsten Solves Capacity Challenges in 3D NAND Device Manufacturing
ALD (atomic layer deposition) controls specific reactant molecules precisely ...
Self-aligned Fin Cut Last Patterning Scheme for Fin Arrays of 24nm Pitch and Beyond
Learn about a FinFET process flow with various fin cut approaches to create a...
Published on April 18th, 2019 by
Coventor
Lithography Challenges For Leading Edge 3D Packaging Applications
Simpler single pass topside test can provide reasonable accuracy for monitori...
Published on April 18th, 2019 by
Veeco
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