Business & Marketing Strategies

Week In Review: Manufacturing, Test

Mark Bohr retires; Intel architecture day; tool forecast

A New Approach to Metrology

Startup has a new leading-edge technology in metrology based on the Hall effect microscopy effect.

Week in Review: IoT, Security, Auto

Arm predictions; Marriott hack; Waymo truck.

Week In Review: Design, Low Power

Royalty-free I3C; CFET parasitic variation modeling; Intel funds analog IP generation.

How to nail functional safety in your next design

Lock step, redundant execution and split-lock—which is better and why.

All About Test (more)

What’s in a Name?

Test Vision 2020 may need a new moniker.

NIWeek Test Talk

National Instruments executives discuss semiconductor testing.

The Best in Test

VLSI Research recognizes leading test vendors.

blog (more)

Looking For The Elephant In The Valley

Female role models doing exceptional things in tech have always existed. Hope...

The Week in Review: IoT

IoT market growth; investments in IoT; Cambium products.

Generically Reusable IP No One Uses

If we just keep putting generically reusable on the box, all we’re doing is...

Blogs - LPHP (more)

How to nail functional safety in your next design

Lock step, redundant execution and split-lock—which is better and why.

Security, Scaling and Power

Why these three things are related and what it means for Intel and the rest o...

Efficient Low Power Verification & Debug Methodology Using Power-Aware Simulation

Making sure subtle bugs do not escape in low power designs.

Blogs - MD (more)

Trade Disputes Increase Market Uncertainty

What a difference a trade war can make.

2 Big Shifts, Lots Of Questions

Why AI, and systems companies designing their own chips, could alter semicond...

What’s The Outlook for Memory?

DRAM and NAND fell off the cliff in '18 with no relief in sight for '19.

Blogs - PTES (more)

4 Issues In Test

This normally quiet segment is boiling over with challenges.

Food for Thought

The good and bad of using technology to modify what we eat.

The Next Materials Race

Why a trade war isn't all bad for the semiconductor materials market.

Blogs - Security (more)

Building Security into the Smart Home Devices with a Hardware Root of Trust

Best practices for protecting personal assets from cyber criminals.

Five steps to successful threat modeling

How to build a security plan and put it into action.

Dawn Of The Data-Driven Age

Making sense of technology directions requires a different starting point.

Blogs - SLD (more)

Methodologies And Flows In A Rapidly Changing Market

The problem isn't the tools. It's the rate of innovation.

Patently Absurd

Sometimes you can find some gems when you dig into the patent system.

Heterogeneous Computing Raises The Bar For Functional Verification

Programmable SoCs are shaping up to be an important part of the semiconductor...

Cascade Effects (more)

What Just Happened?

In the period of a year the semiconductor industry has transformed into somet...

Crunch Time

The network as we've known it for a couple of generations is changing before ...

The “Last Simple Node” And the Internet of Things

A huge amount of foundry space built in the last five years will be converted...

EDA For Manufacturability (more)

Crossing The Chasm: Uniting SoC And Package Verification

EDA companies, OSATs, and foundries must collaborate to ensure wafer-level pa...

Will EUV Kill Multi-Patterning?

Even with EUV in play, i193 multi-patterning may still be the most cost effec...

Edges Of Darkness (more)

Extra! Extra! Read All About It!

ASML is going into the pellicle business!

Visiting The Future At CLEO

Pointing light in different directions: mid-infrared microscopy, quantum cryp...

Advanced Lithography: Moore’s Law Moves On

If designers can stand all the rules that come with quadruple patterning, the...

Foundry Forum (more)

Samsung Foundry’s Business Strategy

A look at manufacturing changes and advanced technology updates.

Hand's On Design (more)

Does IoT Change Design?

Is the Internet of Things really something that will impact system design, or...

EDA Resurgence Through Open Flows

The EDA industry can experience a resurgence if truly open interfaces and ope...

The Perilous Path From Technology To Product

Just because a product can do more doesn’t mean it should—or that you’l...

ImPatterning (more)

3D Construction Ahead

Building sub-wavelength structures using photons, and using 3D printers to cr...

ReRAM Gains Even More Steam

Latest manufacturing techniques are being explored as commercial products beg...

Molecular Imprints becomes a virtual reality company

Remainder of company acquired by Magic Leap, a VC-funded startup led by Google.

Inside Big Data (more)

Is It Safe To Assume That All “Passed” Die Are Actually “Good” Die?

Detecting tricky test escapes and preventing defective parts from getting int...

Are All Known Good Tested Devices Created Equal?

Post-mortem on RMAs backed by Big Data Analytics prove otherwise.

A More Efficient Way To Calculate Device Specs Of Thousands Of Tests For Improved Quality And Yield

Using actual device performance data is a critical safeguard to ensure qualit...

Int News (more)

Siemens To Buy Mentor For $4.5B

Updated: Deal adds mechanical, thermal, electrical and embedded software capa...

Samsung To Buy Harman For $8B

Tier 1 acquisition boosts automotive portfolio.

Qualcomm + NXP = IoT Powerhouse

What the Qualcomm-NXP deal means for IoT.

IoT and Security (more)

Week in Review: IoT, Security, Auto

Arm predictions; Marriott hack; Waymo truck.

Open-Source RISC-V Hardware And Security

Experts at the Table, Part 1: The advantages and limitations of a new instruc...

Building Security into the Smart Home Devices with a Hardware Root of Trust

Best practices for protecting personal assets from cyber criminals.

Knowledge Central (more)

Major Growth For Knowledge Center

An update on the Knowledge Center, plus a few pop quizzes.

Industry Collaboration Starts

Check out all the new stuff...And this is just the beginning.

Welcome To The Knowledge Center

There are more than 1,600 information pages already in the system, and many m...

Litho Guru (more)

Semicon West Lithography Report

OK, so I didn't go to Semicon West. That doesn't mean I don't have opinions ...

SPIE Advanced Lithography 2013 – day 2

There were some great papers at AL on Tuesday.  Here are some of my favorite...

SPIE Advanced Lithography 2013 – day 4

The last day of the conference gave the tool updates. So how is EUV progress...

Low Power-High Performance (more)

How to nail functional safety in your next design

Lock step, redundant execution and split-lock—which is better and why.

Security, Scaling and Power

Why these three things are related and what it means for Intel and the rest o...

What Makes A Chip Design Successful Today?

Maximum flexibility is no longer the reliable path to product success. While ...

Making The IoT Smarter (more)

Getting Ready For The IoT

Preparing for the next seismic shift in the semiconductor industry.

Metrics For Measuring Performance And Power In IoT SoC Designs

Benchmarking can provide relevant data for real-world applications.

The Real Value In Customizing Instructions

How to enable an order of magnitude in power savings for IoT applications.

Manufacturing and Design (more)

Week In Review: Manufacturing, Test

Mark Bohr retires; Intel architecture day; tool forecast

2018 eBeam Initiative Perceptions Survey Results [September 18, 2018]

Confidence in EUV and multi-beam remains high in annual perceptions survey.

Manufacturing Bits: Dec. 11

FinFET vs. FD-SOI pH sensors; 3D ISFETs.

News (more)

Week In Review: Manufacturing, Test

Mark Bohr retires; Intel architecture day; tool forecast

Week in Review: IoT, Security, Auto

Arm predictions; Marriott hack; Waymo truck.

Week In Review: Design, Low Power

Royalty-free I3C; CFET parasitic variation modeling; Intel funds analog IP ge...

On The Edge (more)

Apple Vs. FBI, Take Two

No system can ever be fully secured.

Oh, The Hypocrisy

Did Apple really claim it's protecting the privacy of iPhone customers?

IoE Things Are Spying On Us

Direct marketers are using hiddenware to figure out what we're thinking.

Open Talk (more)

ARM Buys Carbon

Deal allows ARM to create virtual prototypes for performance and power analys...

Customized On-Chip Process Monitors

Using ring oscillators to validate design signoff methodology and silicon pro...

Inside The Hybrid Memory Cube

A look at how to break through the memory bandwidth wall.

Packaging and Test (more)

4 Issues In Test

This normally quiet segment is boiling over with challenges.

Concurrent Test

The growing challenge to do more in the same time window.

Food for Thought

The good and bad of using technology to modify what we eat.

Power Architect (more)

TSMC: 10nm To Be Greater Than 10% Of 2017 Wafer Revenue

10nm heads into full swing, with 7nm and 5nm on the horizon.

Green Computing: GPUs Strike Back

Speed matters, but so does efficiency.

Making Waves In Deep Learning

How deep learning applications will map onto a chip.

Power Down (more)

A Strategy For Designing For Power With FinFETs

Moving from 28nm to finFETs provides a 1.2X improvement in power and performa...

Doing More With RTL Power Analysis: Smart Synthesis Architecture

The migration to finFET processes requires a serious focus on dynamic power c...

Microarchitecture Design For Low Power

A look at first-in, first-out design tradeoffs.

Process Watch (more)

The Economics Of Moore’s Law

Ten years from now, CMOS will seem as old-fashioned as vacuum tubes.

The Internet Of Power Also Benefits From Moore’s Law

It's increasingly possible to stack technologies to produce smart systems.

Betting On Wright’s Law

Moore’s Law is primarily an economic law, but it can be expanded and applie...

Real Insights (more)

Getting A Handle On RTL X-Verification Challenges

Optimistic simulation behavior can hide bugs in your design that don't show u...

Design And Verification Survey Results

New Poll: Lint topped the list on verification technologies to adopt, followe...

Billion-Gate Signoff

A recommended sign off activity list mean fewer re-spins and a design that is...

Research (more)

Manufacturing Bits: Dec. 11

FinFET vs. FD-SOI pH sensors; 3D ISFETs.

System Bits: Dec. 11

AV costs; exchanging quantum information; 3D digitization of objects.

Power/Performance Bits: Dec. 11

Internet of Ears for smart buildings; loose-fitting smart clothing; privacy a...

Round Tables (more)

Open-Source RISC-V Hardware And Security

Experts at the Table, Part 1: The advantages and limitations of a new instruc...

Where Advanced Packaging Makes Sense

Experts at the Table, Part 1: Impact on the supply chain, who's using advance...

IP Tracking and Management

Experts at the Table, part 1: What are the important elements of an IP tracki...

Secure Connections (more)

Brave New World Of Mobility

The ITS World Congress in Bordeaux demonstrates the potential of future mobil...

How To Prevent Identity Theft

The number of choices for securing identities is on the rise, but so is the n...

The Promise Of NFC For Industry 4.0

The manufacturing sector has become increasingly digital, which means it can ...

Setting The Standard (more)

Get Ready For DVCon Europe

New conference will address complex system-level design, mixed signal verific...

2014 Accellera Standards Are Built on Powerful Shoulders

What to watch out for in standards this year and how those changes will affec...

Community, Collaboration And Standards

Where to find standards downloads for the electronics industry and what they'...

Special Reports (more)

The Cost Of Accuracy

Accuracy is a relative term that complicates design and verification. Machine...

Getting Down To Business On Chiplets

Consortiums seek ways to ensure interoperability of hardened IP as way of cut...

Foundries Prepare For Battle At 22nm

Bulk CMOS, FD-SOI and finFETs all on tap as big players vie for differentiati...

Standards And Beyond (more)

Important Changes Ahead

DesignCon panels will focus on system-level power modeling and silicon photon...

See The Internet Of Things…In 3D

The need to integrate a wide variety of functionality economically can't be a...

Multi-Die Packaging Gains Steam

Commercial progress to be unveiled at Global Interposer Technology workshop.

Startup Corner (more)

A New Approach to Metrology

Startup has a new leading-edge technology in metrology based on the Hall effe...

Training a Neural Network to Fall

A cautionary tale of an early attempt to put AI on an IoT system that detects...

AI Accelerator Gyrfalcon Soars Post Stealth

Second generation inference accelerator ASIC targets the datacenter.

System-Level Design (more)

Week In Review: Design, Low Power

Royalty-free I3C; CFET parasitic variation modeling; Intel funds analog IP ge...

Blog Review: Dec. 12

FPGA verification; market rankings; supply chain traceability.

System Bits: Dec. 11

AV costs; exchanging quantum information; 3D digitization of objects.

Technical Papers (more)

Machine Learning Based Prediction: Health Behavior on BP

ML algorithm + individual data = personalized recommendations to reduce blood...

Autonomous Vehicle Navigation in Rural Environments without Detailed Prior Maps (MIT)

Self-driving technology for back roads

Silicon CMOS Architecture For A Spin-based Quantum Computer

UNSW researchers have shown how a quantum computer can be manufactured using ...

The Connected Perspective (more)

2017: A Good Year for ATE

Test equipment sales were up, and so were the share prices of ATE stocks.

That Was The Year That Was In Test

2017 featured a big proposed acquisition.

2017 ITC Wrap-up

News from Advantest, Optimal+, Astronics Test Systems.

The Early Edition (more)

SoC Connectivity Verification Nightmare

Static checks supplement simulation-based verification.

Physical Lint: Physical Quality Metrics For Your RTL

Improving the quality of RTL leads to more predictable design convergence and...

Taming Lint With Formal

Linting tools take advantage of fast and shallow analysis to provide quick fe...

The Engineering Career Blog (more)

Commercializing Technology

Once you develop the product, you have to be prepared to sell it.

A Tough Balancing Act

Should you focus on technology or customers?

Moving From Engineering To Management Or Staying On The Technical Track

The stigma of sticking to your technology roots is gone. So what's your next ...

The Traffic Cop (more)

Three Common SoC Power Management Myths

Approaching power management from the architectural design level.

NoC Versus PIN: Size Matters

Complexity and flexibility are the real drivers of fabric choice, not the num...

Don’t Forget To Consider Productivity In Semiconductor IP Evaluations

Make vs. buy isn't as simple a decision as it might appear.

The Way IC It (more)

CSR In Semis

Giving back to the industry is a good thing—and something everyone should b...

Stacking The Deck

Enabling 2.5D and 3D architecture and the supply chain.

Stacking The Deck

Enabling 2.5D and 3D architecture and the supply chain.

Top Stories (more)

What Makes A Chip Design Successful Today?

Maximum flexibility is no longer the reliable path to product success. While ...

Impacts Of Reliability On Power And Performance

Determinism and coherency are becoming increasingly important as chips are us...

Open-Source RISC-V Hardware And Security

Experts at the Table, Part 1: The advantages and limitations of a new instruc...

Transcendental Specs (more)

It’s All In the Sequence

Whether dealing with SoCs or a disaster in space, determining the correct set...

Making Way For Register Specification Software

While more registers means more functionality and configurability, more is no...

The Ultimate Shift Left

Important observations from Einstein and New England's ice traders.

Uncategorized (more)

Cost Analysis of a Wet Etch TSV Reveal Process

How to scale through-silicon vias and improve industry adoption.

designHUB: Design Reuse Made Real

Why companies need to reassess legacy processes, tools and design management ...

Cure The Common Cold…

...And much more. A call for papers for Arm TechCon.

Videos (more)

Making Sense Of DRAM

What kind of memory is used where and why.

Concurrent Test

The growing challenge to do more in the same time window.

Planarization Challenges At 7nm And Beyond

Why it's becoming harder to prepare a wafer at advanced nodes.

Views From The Fringe (more)

A Semiconductor Approach To Desalination

A new growth market for a very good cause.

Quality And Safety In Automotive Electronics: Venturing beyond ISO-26262

For the automotive market, chips need to last a lot longer than they do in a ...

VoltEdge (more)

Power Shifts In Digital Chip Space

The front runner is Intel, and it’s uncertain if or when anyone will catch up.

Improved Efficiency

What’s ahead in power management techniques and why changes are needed.

Near-Threshold Computing

Operating near the level when transistors switch on an off can save lots of p...

Whitepapers (more)

2018 eBeam Initiative Perceptions Survey Results [September 18, 2018]

Confidence in EUV and multi-beam remains high in annual perceptions survey.

Accurate, fast P2P resistance extraction for unconventional geometries

How to measure interconnect resistance.

Ultra-Low-Power SAR ADC in 22 nm FD-SOI Technology Using Body-Biasing

Explore how an analog-to-digital converter saves power in FDSOI technology.


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