Delivering High-Speed Communications: The Back Story


Back in January, I posted a blog about what it takes to deliver high-speed communication. In that post, I talked about a new test board for our high-speed 7nm 56G PAM4 & NRZ DSP-based long-reach SerDes. We collaborated with several companies to build a high-precision board that could be used to test our SerDes in a system context. At that time, we were just finishing the opening act for thi... » read more

High-Speed Communications: On The Road Again


Lately, we’ve had quite a lot of trade show participation. I discussed ISSCC last month. I will be careful right now to state that ISSCC is a technical conference and not a trade show. The organizers are quite particular about that. Nonetheless, we were invited to demonstrate our high-speed SerDes there, and we got a lot of great questions from a lot of very smart people. Since ISSCC, we... » read more

A Conference For The Ages


The International Solid-State Circuits Conference (ISSCC) was held recently in its permanent location at the San Francisco Marriott Marquis. eSilicon had the honor of both presenting our SerDes capabilities and demonstrating the technology as well. More about that later. First, I’d like to examine the institution called ISSCC. The first ISSCC was held in 1954 in Philadelphia. Yes, 1954, that... » read more

High-Speed Communication Takes A Village


Supply chain, partner network, ecosystem. There are a lot of ways to describe the collection of companies needed to get something done. We’ve all discussed the extensive ecosystem needed to get an advanced chip designed and built. Without a doubt, that is a formidable problem addressed by a sophisticated team of companies. I’d like to take it up a notch in this discussion, however. What abo... » read more

Supercomputers Are For Everyone


Our SerDes world tour continues. This past month, we demonstrated our 7nm 56G long-reach SerDes in Dallas and Israel. In Dallas, our demonstration included error-free operation in 56G PAM4 over a 30dB channel without forward error correction through an eye-popping five-meter cable. Many thanks to our partner Samtec for providing that cable, allowing backplane designers to now “reach beyond th... » read more

High-Speed Serial Comms: Getting There Is Half The Fun


Last month I wrote about our 56G SerDes announcement – silicon validated and running in Rome at a major show. We had a great time at that show and got a lot of compliments about the quality and flexibility of our SerDes. These kinds of unfiltered, unsolicited customer comments are really what makes it all worthwhile. It was a gratifying and exciting time. This month, we’re at it again. O... » read more

56G 7nm SerDes: Eyewitness Account


High-performance SerDes represents critical enabling technology for advanced ASICs. This star IP block finds application in many networking and switching designs as well as other high-performance applications. So, when a new high-performance SerDes block hits the streets, it’s real news. eSilicon has been enjoying the spotlight on such an event. We recently announced silicon validation of our... » read more

Technical Conferences: The Insurmountable Opportunity


As a technology marketeer, I’m always looking for high-leverage events to promote our brand and gain visibility for new products and services. Let’s face it, this is the main benefit for attending a technical conference or a trade show. While the dream might be 40+ leads that are well-qualified and closable in the quarter, the reality is more of a long-game kind of strategy. For years, t... » read more

FinFET ASICs: It Takes A Platform


Sophisticated, specialized ASIC technology is making an impact on the everyday world around us. Whether it’s a gadget you can have a conversation with, a car that will take over driving from time to time, or internet speeds that seem impossibly fast, there is likely sophisticated custom silicon present as a critical enabling technology. Plenty has been written about advanced ASICs for network... » read more

Deep Learning And The Future


Following up from my last post on our deep learning event at the Computer History Museum – “ASICs Unlock Deep Learning Innovation,” I’d like to take a glimpse into the future. Like many such discussions, it’s often useful to take a look back first to try and make sense out of what is to come.  That’s essentlially what our keynote speaker, Ty Garibay, did at the event. Ty is the CTO... » read more

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