Extending The Benefits Of UVM To Include AMS: An Update On Accellera’s UVM-AMS Standard Development

By Tom Fitzpatrick and Peter Grove SoC teams can be divided up into design and verification groups. For digital designs, the Universal Verification Methodology (UVM), initially developed by Accellera and now standardized as IEEE 1800.2, has been the industry standard for the past decade. Since most SoC designs also have analog and mixed-signal IP blocks, it would be ideal for verification en... » read more

Get Ready For DVCon Europe

By Martin Barnasconi DVCon Europe, a new conference and exhibition around design and verification, will be held Oct. 14-15 in Munich, Germany. Call for abstracts for DVCon Europe is open through April 8. The obvious question is why DVCon Europe. DVCon and its predecessor conferences have been held successfully in the Silicon Valley for more than 20 years. The conference is extremely success... » read more

2014 Accellera Standards Are Built on Powerful Shoulders

By Adam Sherer Looking out at the fresh snow coating the landscape here in Buffalo, it’s tempting to look toward 2014 and focus only on the fresh and new. However, if I’ve learned anything about this city from the day I arrived here as a freshman EE in 1984, it’s that you don’t bury your foundation. Instead, you recognize it as your greatest strength, the powerful shoulders upon whic... » read more

Community, Collaboration And Standards

EDA tools/methodologies and semiconductor IP creation are strongly driven by standards. Dating back to the 1980s, standards have helped shape electronic design industry – from the way we design silicon to the way we do business. Indeed, [getentity id="22024" comment="Accellera"] was formed from a merger of two leading standards bodies in the early 1990s, [getentity id="22025" comment="VHDL In... » read more