Reduce 3D-IC Design Complexity: Early Package Assembly Verification


Uncover the unique challenges, along with the latest Calibre verification solutions, for 3D-IC design in this new technical paper. As 2.5D and 3D-ICs redefine the possibilities of semiconductor design, discover how Siemens is leading the way in verifying complex multi-dimensional systems, while shifting verification left to do so earlier in the design process. What you'll learn: Overcom... » read more

Key Critical Specs You Should Know Before Selecting a Function Generator


Selecting a benchtop function generator for your everyday use is very important. You want to be sure it produces the signal types that you need for your tests without introducing unwanted jitters, noise, harmonic distortions, or signal flaws. Introducing unwanted signal flaws inadvertently causes false test rejects due to your function generator. It is a common mistake to purchase the least exp... » read more

Bridging the Gap Between Industry and Academia


The purpose of the Cadence Academic Network is to promote the proliferation of leading-edge technologies and methodologies at universities renowned for their engineering and design excellence in the areas of verification, design, and implementation of microelectronic systems. Taking a four-pronged approach of recruiting, promoting the Cadence university software program, establishing academic p... » read more

Blog Review: April 24


Cadence's Vatsal Patel notes the factors that make high-bandwidth memory ideal for AI, such as improved bandwidth and area from vertical stacking and power reduction features like data bus inversion. Synopsys' Rob van Blommestein points to early power network analysis as a way to ensure that enough power is delivered to each transistor to mitigate potential power-related issues within the ch... » read more

Rigorous Correlation Methodology for PCIe 5.0 & PCIe 6.0 DSP Based IBIS-AMI Models


IBIS-AMI models have been around for a decade and evolved to provide off-chip and system designers an efficient way to assess link performance of high-speed electrical interfaces with transceivers implementing various combination of equalization techniques [1]. As with any model, for IBIS-AMI to be useful they need to be benchmarked and carefully correlated to real-world silicon performance of ... » read more

How To Scale Application Security Across The Enterprise


Enterprise organizations have hundreds of developers on numerous teams in dozens of business units. They are all working on thousands of applications, releasing software in very rapid iteration cycles. The challenges of development across all these software development life cycles, business units, and organizational silos are well known, and the sheer scale of enterprise development multiplies ... » read more

Aeonic Generate GGM High Performance SoC Clock Generation Module


Core counts have been increasing steadily since IBM's debut of the Power 4 in 2001, eclipsing 100 CPU cores and over 1,000 for AI accelerators. While sea of processor architectures feature a stamp and repeat design, per-core workloads aren't always going to be symmetrically balanced. For example, a cloud provider (AI or compute) will rent out individual core clusters to customers for specialize... » read more

Blog Review: April 17


Siemens' Sumit Vishwakarma highlights the importance of crystal oscillators to the proper functioning of many semiconductor devices and applications, from clock signals to transmission and reception of radio waves. Cadence's Jay Domadia introduces some of the new features in GDDR7, such as a semi-independent row and column command address bus and two modes of data signaling, enabling PAM3 fo... » read more

Blog Review: April 10


Cadence's Shyam Sharma looks at the evolution of the LPDDR standard and finds that LPDDR5X is opening new specialized markets for low-power DRAMs beyond the traditional areas of mobile, IoT, and automotive. Siemens' Hossam Sarhan and Dusan Petranovic find that new physical verification approaches are needed to ensure the performance and reliability of superconducting ICs and introduce a hybr... » read more

NoCs In 3D Space


A network on chip (NoC) has become an essential piece of technology that enables the complexity of chips to keep growing, but when designs go 3D, or when third-party chiplets become pervasive, it's not clear how NoCs will evolve or what the impact will be on chiplet architectures. A NoC enables data to move between heterogeneous computing elements, while at the same time minimizing the resou... » read more

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