Suppressing Power Side-Channel Attacks: A HW/SW Design For Resource-Constrained IoT Devices


A technical paper titled “Hardware/Software Cooperative Design Against Power Side-Channel Attacks on IoT Devices” was published by researchers at Tokyo Institute of Technology and the University of Electro-Communications. Abstract: "With the growth of Internet of Things (IoT) era, the protection of secret information on IoT devices is becoming increasingly important. For IoT devices, atta... » read more

K-Fault Resistant Partitioning To Assess Redundancy-Based HW Countermeasures To Fault Injections


A technical paper titled “Fault-Resistant Partitioning of Secure CPUs for System Co-Verification against Faults” was published by researchers at Université Paris-Saclay, Graz University of Technology, lowRISC, University Grenoble Alpes, Thales, and Sorbonne University. Abstract: "To assess the robustness of CPU-based systems against fault injection attacks, it is necessary to analyze the... » read more

An Analytical EM Model For IC Shielding Against HW Attacks


A technical paper titled “Refined Analytical EM Model of IC-Internal Shielding for Hardware-Security and Intra-Device Simulative Framework” was published by researchers at Bar-Ilan University and Rafael Defense Systems. Abstract: "Over the past two decades, the prominence of physical attacks on electronic devices, designed to extract confidential information, has surged. These attacks exp... » read more

White-Box Fuzzer With Static Analysis To Detect And Locate Timing Vulnerabilities In RISC-V Processors 


A technical paper titled “WhisperFuzz: White-Box Fuzzing for Detecting and Locating Timing Vulnerabilities in Processors” was published by researchers at Indian Institute of Technology Madras, Texas A&M University, and Technische Universität Darmstadt. Abstract: "Timing vulnerabilities in processors have emerged as a potent threat. As processors are the foundation of any computing s... » read more

HW Security Bug Characteristics in Google’s OpenTitan Silicon Root Of Trust Project 


A technical paper titled “An Investigation of Hardware Security Bug Characteristics in Open-Source Projects” was published by researchers at NYU Tandon School of Engineering and University of Calgary. Abstract: "Hardware security is an important concern of system security as vulnerabilities can arise from design errors introduced throughout the development lifecycle. Recent works have pro... » read more

Security Threats To Multitenant FPGAs: A Remote Undervolting Attack That Activates A Trojan Concealed Within A Victim Design 


A technical paper titled “X-Attack 2.0: The Risk of Power Wasters and Satisfiability Don’t-Care Hardware Trojans to Shared Cloud FPGAs” was published by researchers at EPFL, Cyber-Defence Campus (Switzerland), and Northwestern Polytechnical University (China). Abstract: "Cloud computing environments increasingly provision field-programmable gate arrays (FPGAs) for their programmability ... » read more

Challenges And Innovations Of HW Security And Trust For Chiplet-Based 2.5D and 3D ICs


A technical paper titled “On hardware security and trust for chiplet-based 2.5D and 3D ICs: Challenges and Innovations” was published by researchers at STMicroelectronics Crolles (ST-CROLLES), Département Systèmes et Circuits Intégrés Numériques (DSCIN), Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), and Laboratoire Systèm... » read more

SystemC-based Power Side-Channel Attacks Against AI Accelerators (Univ. of Lubeck)


A new technical paper titled "SystemC Model of Power Side-Channel Attacks Against AI Accelerators: Superstition or not?" was published by researchers at Germany's University of Lubeck. Abstract "As training artificial intelligence (AI) models is a lengthy and hence costly process, leakage of such a model's internal parameters is highly undesirable. In the case of AI accelerators, side-chann... » read more

Nanoscale Reconfigurable Si Transistors (TU Wien, CNRS, UNC)


A new technical paper titled "Nanoscale Reconfigurable Si Transistors: From Wires to Sheets and Unto Multi-Wire Channels" was published by researchers at TU Wien, CNRS, and University of North Carolina at Chapel Hill. Abstract: "In this work, bottom-up Al–Si–Al nanowire (NW) heterostructures are presented, which act as a prototype vehicle toward top-down fabricated nanosheet (NS) and ... » read more

FeFET Memory Encrypted Inside The Storage Array


A new technical paper titled "Embedding security into ferroelectric FET array via in situ memory operation" was published by researchers at Pennsylvania State University, University of Notre Dame, Fraunhofer IPMS, National University of Singapore, and North Dakota State University. Abstract "Non-volatile memories (NVMs) have the potential to reshape next-generation memory systems because of... » read more

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