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Automated Chip Polishing Can Make Your Design Shine


Today’s modern chip design is a collaboration among many design teams, often using different design flows and different EDA tools. This state of the chip design industry can create high risk in the layout process, forcing delays in product release. To help reduce this risk, many levels of verification throughout the design flow exist to identify problematic areas in a design. While new EDA to... » read more

Are Three Eyes Better Than Two?


It is clear that having two eyes is better than having just one. Not only is depth perception much better, but we get to enjoy 3D movies because of it. There is also some sense of security in knowing that if something terrible happened to one eye, you always have a backup. Have you ever wondered if these sorts of advantages are extendable? You’ve probably heard the phrase about someone ha... » read more

Capacity Constraints And DFM At Mature Nodes


We’re witnessing an interesting phenomenon in the SoC segment of the semiconductor industry today. One might call it the “forced waterfall effect.” What I’m referring to is the tendency for production at semiconductor nodes older than the leading edge to be under long-term foundry capacity constraints. Normally this occurs with the “hot process node,” that is, the leading edge wh... » read more

Balancing On The Color Density Tightrope


Balancing on wobbly tightropes is something that chip designers get pretty good at. For instance, there is a fine balance between optimizing performance and minimizing leakage in a design layout. Dealing with the new requirements that multi-patterning (MP) introduces into a design flow creates many new tightropes to walk. I tiptoed out on one of the rarely talked about ones in my last article... » read more

Rule Deck Comparison Doesn’t Have To Be Difficult


Foundry rule decks change all the time, as foundries uncover new manufacturing issues, or the process changes, or design criteria are tightened to improve runtime or stability. Sometimes new versions of a user’s design rule checking (DRC) tool are released, and the results from the DRC run differ from the previous version. Or perhaps a company wants to compare results between rule decks from ... » read more

Multiple Patterns, Multiple Trade-Offs


As the saying goes, “There is no such thing as a free lunch.” That is a reality that chip designers have had to live by from the beginning. From the advent of the first design rule, it was clear that you couldn’t just do anything you wanted. In the end, everything comes down to trade-offs. Whether it’s area, speed, leakage, noise sensitivity, or drive current, doing something to impr... » read more

Fill Database Management Strategies At Advanced Nodes


Fill has been around for many nodes, and was originally introduced to improve manufacturing results. The foundries learned that by managing density they were able to reduce wafer thickness variations created during chemical-mechanical polishing (CMP) processes, so they introduced density design rule checks (DRC). To meet these density requirements, designers “filled” open areas of the layou... » read more

Is Multi-Patterning Good for You?


I think we can all remember growing up and our parents making us take nasty-tasting medicines, or eat foods we didn’t like, or endure painful things like shots, all under the banner of “It is good for you!” We didn’t like it then, and we still don’t like it as adults. We would all prefer a way to lose weight while eating anything we want, or building strong muscles and aerobic health ... » read more

The Route To Faster Physical Verification And Better Designs


By Nancy Nguyen & Jean-Marie Brunet As we’ve moved to today’s leading-edge nodes, physical layout designers have faced more and more challenges to get their design to tape-out on schedule. Timing becomes increasingly difficult to converge, power reduction for both IR and leakage becomes a big issue, and most importantly, how do we meet all of the ever-growing and more complex signoff d... » read more

Self-Aligned Double Patterning—Part Deux


In my last article, I introduced you to the basic Self-Aligned Double-Patterning (SADP) process that is one of the potential candidate techniques for processing metal layers at 10nm and below, but let’s have a quick recap. SADP uses a deposition and etch step process to create spacers surrounding a patterned shape (Figure 1). As you can see, there are two masking steps—the first mask is cal... » read more

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