category: EDA For Manufacturability

category: IoT, Security & Automotive

You Ain’t Seen Nothing Yet
By David Abercrombie - 19 Sep, 2013 - Comments: 1

I’ve been talking about double patterning for a long time now in this series of blogs. I thought it might be good to start looking ahead at what is next for multi-patterning (Don’t Panic!). As you may have been hearing or reading, it doesn’t look like EUV lithography is going to be ready for 10nm, and may not even make it for 7nm. This means that alternative methods of extending the exist... » read more

I Just Want Closure!
By Jean-Marie Brunet - 15 Aug, 2013 - Comments: 0

By Jean-Marie Brunet We all know it by now, but let’s say it one more time for the cameras—the level of complexity of closure at 20 nm and below is considerably higher than for any previous nodes. While the migration of manufacturing requirements into design started with a few suggested activities at 65 nm, such as recommended rules compliance, lithography checks, and critical area analysi... » read more

You Can’t Get There From Here
By David Abercrombie - 17 Jul, 2013 - Comments: 0

By David Abercrombie In my last article, I reviewed the aspects of cell design that are affected by double patterning (DP). This time, I’ll discuss how automatic routing is affected by DP. Let’s begin by looking at the interaction between decisions made at the cell design level and decisions made at the routing level. One key routing decision is whether or not you will allow cell-to-cel... » read more

Let’s All Meet At The Via Bar!
By Jean-Marie Brunet - 30 Jun, 2013 - Comments: 0

By Jean-Marie Brunet At 28 nm and below, a variety of new design requirements are forcing us to adjust the traditional layout and verification process of digital designs. The use of vias, in particular, has been significantly impacted. New via types have been introduced, and the addition of double patterning, FinFETS, and other new design techniques has not only generated a considerable increa... » read more

Between A Rock And A Hard Place
By David Abercrombie - 16 May, 2013 - Comments: 0

By David Abercrombie My previous articles included a lot of discussion about correcting error violations in double patterning (DP). This time let’s take a step back up the design flow. DP requires a design team to make some important decisions about standard cell design methodologies, or risk running into serious placement issues down the line. Understanding why this is so, and what your opt... » read more

Chasing Rabbits
By David Abercrombie - 21 Mar, 2013 - Comments: 0

“Now, here, you see, it takes all the running you can do, to keep in the same place. If you want to get somewhere else, you must run at least twice as fast as that!” —Lewis Carroll, Through the Looking Glass By David Abercrombie As I discussed in my previous article, the use of stitching can greatly reduce the number of double patterning (DP) decomposition violations that a designer ... » read more

A New World For Fill At N20
By Mentor Graphics Staff Writers - 21 Feb, 2013 - Comments: 1

By Jeff Wilson and Jean-Marie Brunet There are many drastic changes required to design, verify, and manufacture semiconductors at the 20nm process node (N20). One of these is fill. At previous design nodes, fill was used just to ensure manufacturability by giving each layer (metal, poly, diffusion) an accepted density. At N20, fill is used to address many more manufacturing issues, and has bec... » read more

Hospital Privileges
By David Abercrombie - 24 Jan, 2013 - Comments: 0

By David Abercrombie In our double patterning (DP) conversations so far, we’ve discussed what it means to decompose a single layer into two masks, and identified typical configurations of polygons that can cause DP violations. We specifically discussed the most common odd cycle violations, and how to fix them by increasing the spaces between polygons. The reality, though, is that no matter h... » read more

Eco-Friendly Strategy
By Mentor Graphics Staff Writers - 12 Dec, 2012 - Comments: 0

By Jeff Wilson If you want a winning fill solution at 20nm, you need a robust ecosystem in place with three main players. Each player has a specific role and, particularly as the new technology is defined, the players need to work in close partnership. Why is the ecosystem so important at 20nm? Because of the technological challenges, including process variability and design complexity. The... » read more

Why Do My DP Colors Keep Changing?
By David Abercrombie - 15 Nov, 2012 - Comments: 0

By David Abercrombie At 20nm, foundries are using several different double patterning design flows. One of the more common flows does not actually require the design team to decompose their layers into two colors. The designer only has to verify that the design can be decomposed before taping out each single layer. There are certain obvious advantages to this flow. For example, the designer do... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2024 SMG   |  Terms of Service  |  Privacy Policy