A next-generation approach to a traditionally time-consuming problem.
While semiconductor verification techniques have evolved considerably over the last 25 years, the debug of design problems found during verification has barely changed. New algorithms including machine learning, visualization approaches, and problem solving ideas allow a different approach to debug that saves up to an order of magnitude in debug time. Vtool has introduced Cogita, a next-generation debug solution that enables a holistic and automated methodology, allowing engineers to track down the root cause to problems in an efficient and error-free manner. Cooperating with existing debug environments, Cogita is particularly effective on large-scale designs verified using emulation and regression simulation, offering significant improvements right across the verification process.
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