Getting Ahead With Early Power Analysis

Today’s mobile applications need to cater to a broad set of applications. They can be communications-heavy (Bluetooth and GPS), graphics-intensive (streaming 4K videos), or compute-intensive workloads (AR/VR gaming).

At the heart of this processing lies the all-powerful mobile processor, which includes a multi-core CPU, GPU, memory and other IP and subsystems for performing a variety of tasks. They can be used for streaming large videos with ultra-HD resolution, capturing sharp photos in poor light, navigating paths to various places, or providing faster performance and more multi-tasking capabilities for executing a variety of different tasks at different times—or more at the same time. It is not uncommon to see activities such as social media newsfeed updates, music streaming and web browser applications running concurrently on a mobile device.

But mobile devices are power-source limited, and that drives the need for ultra-low power design solutions and architectures. Greater functional integration and higher switching speed of finFET devices increase the dynamic power consumed by the chip. They also widen the ‘power gap,’ which is the difference between the amount of power a battery can supply and the amount of power required for reliable operation of the devices.

The result is reduced battery life and degraded thermal performance, which is why designing for low power is so critical. Recognizing the value of addressing power issues early in the RTL design phase, designers are getting creative in tackling this rise in power.

Being early with power
Power needs to be considered as early as possible in the design cycle. Schedule and cost are both severely impacted when design issues are uncovered later in the flow. By making power-related decisions during the architecture phases, the potential for power savings is maximized. Unlike post-synthesis, where the design is decomposed into a sea of gates, higher-level abstractions describe the design at the function level that provide visibility to uncover high-impact changes.

RTL power vs. gate power accuracy is a key concern that is often raised. State of the art front-end power solutions can bridge the gap between RTL power and sign-off numbers by accounting for physical effects such as clocks and wire capacitance, while delivering 20X faster turnaround time when compared to traditional gate-level methodologies. This enables designers to identify and make power decisions early and reliably.

Designing for power efficiency
All of this becomes more critical at 16/14nm and below. Increased device density in advanced finFET technology nodes results in increased power density, causing mounting power and thermal concerns. For instance, according to IBM, 5nm technology offers 40% increased performance or 75% lower power for the same performance when compared to commercial 10nm chips.

To deliver greater functionality at lower power, it is important to ensure the RTL is designed to be power-efficient. By uncovering power reduction opportunities, such as hierarchical clock gating through RTL techniques, powerful interactive debug and power-efficiency metrics, power savings of up to 70% can be achieved.

Using differential energy analysis at RTL to optimize GPU performance/watt
Click on the ANSYS/Qualcomm webinar to learn how Qualcomm’s Adreno GPU, a product of Qualcomm Technologies, leverages early register-transfer level (RTL) power analysis methodologies for optimizing the power efficiency of circuit design. These GPUs accelerate the rendering of complex geometries to deliver high-performance graphics and offer a rich user experience with low power consumption. Thermal constrained performance is a key performance indicator (KPI) for these GPUs.

In this webinar, Qualcomm will demonstrate its successful workflow based on a unique RTL methodology that applies differential energy analysis using ANSYS PowerArtist to identify opportunities for power optimization in its GPUs. The key premise is that the energy required to perform a function remains constant independent of the time it takes for the function to execute. The power increases if the same function is executed in less time but the energy remains constant. If the energy does not remain constant, this is an indication of energy inefficiency in the design. Differential analysis also works well during RTL design phase since relative analysis is less dependent on absolute accuracy.

Figure 1: Differential Energy Analysis for Improved Performance/Watt in Mobile GPU (Reference: Yadong Wang, Qualcomm, Design Automation Conference 2018)

Register here to learn all the details of this high-impact methodology on August 23 at 9 a.m. U.S. Pacific time.