System-Level Design

HEVC Codec Analysis: Exploring the Parallelization Features of SLX

How running a parallelization check can speed up analysis of a HHI/ Fraunhofer reference HEVC codec implementation.


This white paper details the results of running the parallelization features of SLX to quickly explore the HHI/ Fraunhofer reference HEVC codec implementation.

The codec allows developers to make trade-offs of coding efficiency versus effective use of the parallel computation resources of the target platform. SLX is primarily used to assess the benefits of any exposed parallelism in the current implementation.

The presented results are based on the unedited implementation of the code as downloaded on a virtual hexacore target platform based on ARM Cortex A7 processors.

In a test period of 4 hours of computer run time, the speedup results are shown with the default implementation. For an additional 32 loops, opportunities for further parallelism with its associated potential speedup on the target platform were identified including the inhibiting reason. Overall, SLX quickly identifies where manual efforts should be invested or avoided. This case study on unchanged, real-life application source code shows the significant productivity increase by using automation versus a costly, manual investigation by parallelism experts.

Read more here.

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