Achronix is a privately held fabless corporation based in Santa Clara, California and offers high-performance FPGA solutions. Achronix’s history is one of pushing the boundaries in the high-performance FPGA market. Achronix offerings include programmable FPGA fabrics, discrete high-performance and high-density FPGAs with hardwired system-level blocks, data center and HPC hardware accelerator boards, and best-in-class EDA software supporting all Achronix products.

Lead Engineer
Requisition No.:
Type of Position:
Regular, Exempt
Reports to:
Sr. Manager, Hardware Engineering
Bangalore, India

Job Description/Responsibilities
Primary Responsibilities:
The employee will be responsible for module and integration-level RTL verification as well as performance modeling for Achronix’s Speedcore and Speedster FPGA products. The employee is expected to take independent ownership of complex design challenges, which will include the following:

Lead methodology development
Lead verification planning
Functional verification at module-level and full chip-level
Testbench design
Lead ATE functional vector generation
Post-Si support
Provide technical leadership to other engineers
Support front-end management with resource allocation and scheduling
Day-to-day planning and reviews of work completed by junior engineers
The employee is also expected to participate regularly in interactions with global teams spanning Systems, Software, and Product Engineering

Expertise in verification methodologies, especially OVM/UVM
Strong automation and scripting experience, especially in Python and/or Perl
Experience with post-Si bring-up and debug
Very strong verbal and written communication skills
Ability to work in a dynamic and fast-paced environment with a proactive mindset
Prior experience with providing technical leadership to 5-10 member teams
Strong knowledge of DDR/GPIO PHYs and memory controllers or high-speed serial link protocols (such as PCIe, Ethernet, SATA, XAUI etc.) is a big plus
Experience with formal verification tools is a plus

Preferred BS/MS and 9+ years of experience in RTL design and verification
Previous experience in at least 5-6 product developments, including post-Si bring-up