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Achronix

Achronix is a privately held fabless corporation based in Santa Clara, California and offers high-performance FPGA solutions. Achronix’s history is one of pushing the boundaries in the high-performance FPGA market. Achronix offerings include programmable FPGA fabrics, discrete high-performance and high-density FPGAs with hardwired system-level blocks, data center and HPC hardware accelerator boards, and best-in-class EDA software supporting all Achronix products.

Title:
Senior Staff Engineer
Requisition No.:
6400-1030
Type of Position:
Regular, Exempt
Reports to:
Sr. Director, India Technology Centre
Location:
Bangalore, India

Job Description/Responsibilities
Primary Responsibilities:
The employee will be responsible for the ASIC DFT architecture and design of Achronix’s FPGA products in TSMC’s 16nm and 7nm as well as other foundries. The employee is expected to take complete ownership of multiple complex design and flow challenges, which include:

Methodology development/enhancements
DFT architecture of Achronix’s standalone chips and IPs
Planning, implementation, and verification of scan chains for all blocks and the full chip
RTL modifications to enable DFT architecture
ATPG test vector generation and coverage optimization
GLS for test timing verification
Debug and support for ATE testing
Providing technical leadership to the team
The employee is expected to lead interactions with design and fabrication partners, and to mentor other engineers and new hires.

Skills:
Expertise in all DFT concepts and methodologies: compression techniques, OCC, scan-based DFT methodology, chip-level DFT architecture development and verification, ATPG vector generation, and boundary scan chain implementation
Expertise with DFT tools like Tetramax and DFTCompiler/DFTMax, and/or Fastscan
Strong understanding of STA concepts and constraints development
In-depth understanding of synthesis and the scan chain insertion flows therein
Hands-on ability with RTL coding, especially for DFT architecture implementation
Strong programming knowledge in Perl, Tcl, and/or Shell scripting
Experience with flow and automation development
Participated in at least 2 tapeouts on 40nm and below with significant experience on 28nm and below nodes
Strong communication skills
Innovative and out-of-the-box thinking is critical to this role
Good knowledge of JTAG and TAP design
Hands-on experience with non-scan-based DFT methods is a big plus

Experience/Education:
Previous experience in 5-6 VLSI projects in deep submicron technologiesExperience with post-Si debug and understanding of tester constraints is a must
Experience in 28nm and below
Expertise in DFTCompiler, DFTMax and Tetramax is a plus
Preferred BS/MS and 9+ years of experience in DFT and/or related