Achronix is a privately held fabless corporation based in Santa Clara, California and offers high-performance FPGA solutions. Achronix’s history is one of pushing the boundaries in the high-performance FPGA market. Achronix offerings include programmable FPGA fabrics, discrete high-performance and high-density FPGAs with hardwired system-level blocks, data center and HPC hardware accelerator boards, and best-in-class EDA software supporting all Achronix products.

Manager of Verification
Requisition No.:
Type of Position:
Regular, Exempt
Reports to:
Sr. Manager, Hardware Engineering
Bangalore, India

Job Description/Responsibilities
Primary Responsibilities:
The employee will be responsible for leading the hardware verification team that covers module and integration-level RTL verification as well as performance modeling for Achronix’s Speedcore and Speedster FPGA products. The employee is also expected to take hands-on responsibilities for some of the most complex verification tasks. The employee’s responsibilities include the following:

Manage the verification team, including setting of responsibilities, assigning of tasks, reviewing performance, and ensuring technical growth
Lead methodology development
Lead verification planning
Perform own functional verification at module-level and/or full chip-level
Testbench design
Lead ATE functional vector generation
Post-Si support
Provide technical leadership to junior engineers
Support senior management with resource allocation and scheduling
The employee is also expected to participate regularly in interactions with global teams spanning Systems, Software, and Product Engineering

Experience leading a group of engineers either technically, managerially, or both
Expertise in verification methodologies, especially OVM/UVM
Strong automation and scripting experience is a plus
Experience with post-Si bring-up and debug
Very strong verbal and written communication skills
Ability to work in a dynamic and fast-paced environment with a proactive mindset
Strong knowledge of either DDR/GPIO PHYs and memory controllers, or high speed serial link protocols (PCIe, Ethernet, SATA, XAUI, etc.) is a big plus
Experience with formal verification tools is a plus

Preferred BS/MS and 10+ years of experience in RTL design and verification
Previous experience in at least 5-6 product developments, including post-Si bring-up