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Achronix

Achronix is a privately held fabless corporation based in Santa Clara, California and offers high-performance FPGA solutions. Achronix’s history is one of pushing the boundaries in the high-performance FPGA market. Achronix offerings include programmable FPGA fabrics, discrete high-performance and high-density FPGAs with hardwired system-level blocks, data center and HPC hardware accelerator boards, and best-in-class EDA software supporting all Achronix products.

 

Position Profile Name:
SerDes Protocols Applications Engineer
Requisition No.:
7800-1007
Type of Position:
Regular, Exempt
Reports to:
Sr. Director of Product Applications
Location:
Santa Clara, California

Contact:
[email protected]

Job Description/Responsibilities
Ownership of the hard and soft protocol IP used in Achronix products.
Drive cross-functional bring-up, validation, support and documentation efforts of the SerDes and protocol solutions on the Speedster7t devices and boards. The protocols include PCIe Gen3/4/CCIX and 400G Ethernet.
Plan, drive, implement and publish interoperability results for Achronix protocol IP and work with customers to deploy similar solutions on their own systems.
Work with the Achronix software team to implement and verify appropriate protocol macros/configurations for ACE users.
Generate bring-up and reference designs, including simulation support, to highlight protocol use-models and demonstrate performance to customers.
Provide a high-level of technical support to resolve challenging customer issues with a focus on, but not limited to, SerDes and protocol IP.
Participate in road-mapping and planning discussions for SerDes and protocols in future Achronix products.

Required Skills
Expert knowledge of protocol IP with emphasis on, but limited to, PCIe Gen3/4/CCIX and 10G/40G/100G/400G Ethernet.
Understanding of other protocols including Interlaken, FibreChannel and JESD204 is a plus.
Proficient in technical writing, including user guides, test/verification plans and spreadsheet based analyses.
Strong logic design and verification background with experience in STA.
Experience with FPGA implementations and programming, specifically pertaining to SerDes and protocols.
Verilog expertise; System Verilog and VHDL knowledge is a plus.
Good communication skills and ability to multi-task.

Education and Experience
Bachelor’s or Master’s degree in EE, CE or equivalent work experience
At least 5 years’ experience working on protocol IP bring-up, validation and debug.
Expert with lab test equipment, specifically those needed for protocol IP validation, characterization and compliance – oscilloscopes, function generators, logic analyzers, BERTs, backplanes, interposers etc.