What will I be accountable for?


As a Design Verification Engineer, you would be accountable for verification of one or more functional blocks at the unit or top level. Typical accountabilities include:


· Develop SystemVerilog/UVM based testbenches for unit/top level.

· Build and maintain detailed verification plans.

· Generate and run test cases on logic simulation models.

· Debug functional errors in the RTL model using simulation and debug tools with an in-depth understanding of the microarchitecture.

· Define and implement functional coverage.

· Analysis of data from simulation runs using machine learning and data science techniques to drive efficient bug discovery and debug.

· Promote and demonstrate the Arm Core Beliefs and Behaviors.

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