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Arm

As a member of our cache coherent interconnect team, you will be working on design verification methodology improvements which will enable hardware verification across our complete suite of interconnect products.

 

What will I be accountable for?

Drive and initiate verification methodology improvements.
Investigate and review both internal and external solutions to implement solutions in the areas of simulation performance, data visualization and productivity.
Partner with other methodology teams and engineers to ensure best in class solutions.
Debug SystemVerilog/UVM based test benches across both unit and top level.
Promote and demonstrate the Arm Core Beliefs and Behaviors.

For additional details and most recent updates, hit “Apply for job”