As a Memory System / Interconnect Design Engineer, you will be part of the Systems and Software team focused on next-generation interconnects targeting high-end mobile, networking, and enterprise markets. You will contribute to the specification, microarchitecture and RTL design of high-performance, energy-efficient interconnects. This opportunity is specific to a confidential project, and as part of this small and talented team, you will be able to expand your technical breadth relating to leading-edge interconnects, including multi-chip, IO acceleration, and new memory technologies. In addition, your close collaboration with other Austin-based CPU and System IP engineering teams leads to complete IP solutions to address the performance, power and cost requirements for almost all application markets.

What will I be accountable for?

As an RTL Design Engineer, you would be accountable for one or more functional blocks of the Interconnect while working closely with performance modeling, validation, and implementation teams to meet all functional requirements and performance, power, area (PPA) goals. Typical accountabilities include:

Understanding the high-level specification and requirements of one or more functional blocks of the Interconnect
Define the Micro-architecture for the blocks
Develop Verilog RTL logic design for the blocks
Collaborate with verification team on the test plan development for the blocks and verification closure
Debug functional or performance issues with the RTL using simulation and debug tools
Analyze synthesis/timing reports, identify and address critical areas to meet the PPA targets

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