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Arm

As a Design Verification Engineer, you would be accountable for verification of one or more functional blocks at the unit or top level. Typical accountabilities include:

 

· Develop SystemVerilog/UVM based testbenches for unit/top level.

· Build and maintain detailed verification plans.

· Generate and run test cases on logic simulation models.

· Debug functional errors in the RTL model using simulation and debug tools with an in-depth understanding of the microarchitecture.

and more…

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