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Arm

You will be encouraged to build implementations of Arm CPU/GPU class designs using PDG’s optimized physical IP.
The process involves RTL setup, integration of memory models, creation of floorplans and finding the rewarding recipe of synthesis / P&R flow.
The primary objective would be to optimize performance, power and area as required by the Arm IP and the associated market segment.
In terms of backend closure, you will need to take the design through STA, EM, IR drop, signoff DRC and other types of verification steps.
There are lighter aspects related to DFT(scan insertion, compression and ATPG) and Gate-level simulations to report power.
Your daily job will demand a lot of handshaking with physical IP teams who are responsible for “optimized” standard cell and memories.
There is a need to engage with EDA partners in an independent manner to create and deploy recipes related to EDA tools.
You will see exposure to commercial teams at Arm. This will extend to end customers also as you evolve over time.
Interacting with end customers directly to help them in usage of POP IP through the complete customer product tape-out cycle.
Encouraged to drive experiential learning sessions with wider audiences.

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