This is a unique opportunity to be part of the Arm Chandler, Arizona Design Center. Through teamwork, training and dedication to personal development, our goal is that our engineer quickly learns about different aspects of developing highly-complex designs, starts contributing to different project tasks and ultimately develops into an expert in the field. You will be part of engaging, hardworking, and creative team that will provide a fascinating opportunity to innovate and make a meaningful contribution. As part of the verification team, you will be using leading-edge verification technologies and methodologies to ensure the highest quality in our products.


What will I be accountable for?

Working closely with the RTL design team to develop comprehensive block-level verification strategies for the CPU pipeline, memory system, or CPU integration sub-system.

Developing SystemVerilog/UVM testbenches for block-level functional verification

Developing detailed verification plans for the processor block/unit

Debugging and correcting functional errors in the RTL model, using simulation tools, debug tools, and programming skills, based on an in-depth understanding of the architecture and RTL design of the processor

Defining and implementing functional coverage, and enhancing the testbench to ensure coverage closure

Documenting test plans and testbench design
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