Job Description
Arm Physical Design Group (PDG) delivers the most comprehensive and advanced physical IP solution allowing the implementation of complex SoC designs. What Arm PDG offers is the oldest and most widely used in the industry and includes logic IP, Standard Cell, Embedded Memory Compilers, Interface IP and Processor Optimization Pack (POPs). All of the Arm physical IP products are specifically optimized for each foundry and process technology from 250nm to 7-5nm semiconductor processes for various foundries and IDMs.

The Digital IPs, Reference Design and Validation (DRV) group engages in the validation of the library products offered by ARM Physical Design Group on Silicon. We design on test chips aimed to validate IP products (logic libraries, memories, IOs, Analog blocks, System IPs) for cutting-edge semiconductor processes (viz. >90nm, 90nm, 65nm, 40nm, 32nm, 28nm ,14nm and 7nm) for various leading foundries and IDMs around the world. We then characterize and test the silicon dies built by the foundries. These IPs are used by SOC companies & integrated in their design. It is imperative to validate them, to confirm their functionality to customers.

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