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Arteris IP

As a Senior Design Verification Engineer at Arteris, you will work with an expert team to design and deliver interconnect & memory hierarchy solutions for some of the world’s most sophisticated mobile, telecom, automotive, and consumer SoC designs.

You will create designs in a powerful language that blends traditional RTL with leading-edge software to provide extremely configurable, testable, and high-quality solutions. You will go home at the end of the day amazed at all the places where your creations end up.

You will have the opportunity to be part of a proven-successful startup, and to influence development environment, architecture, verification, and everything in-between – you will no longer be stuck in a silo or just a cog in the machine. Your co-workers will be an experienced team of industry experts that love what they do.

Key Responsibilities:

Advanced UVM based test bench development and debugging
Defining, documenting, developing, and executing RTL verification test/coverage at system level
Performance verification and power-aware verification
Triaging Regressions, Debugging RTL designs in Verilog and System Verilog
Help improve and refine verification process, methodology, and metrics
UVM expertise on complex SoC projects from test bench development to verification closure

For additional details and most recent updates, hit “Apply for job”