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Arteris IP

As a Senior Validation Engineer at Arteris IP (Magillem IP Deployment Division), you will be a key player in the validation of our leading System on Chip (Soc) RTL design environment.

You will have the opportunity to be part of a proven-successful startup, and to influence development environment, architecture, verification, and everything in-between – you’ll no longer be stuck in a silo or just a cog in the machine.

Your co-workers will be an experienced team of industry experts that love what they do.

We work under an agile methodology, in continuous integration, and use GIT, JIRA and Confluence.

 

For more & updated details, hit “Apply for job”