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  • U.S.

Arteris IP

Key Responsibilities:

Advanced UVM based test bench development and debugging
Defining, documenting, developing and executing RTL verification test/coverage at system level
Performance verification and power-aware verification
Triaging Regressions, Debugging RTL designs in Verilog and SystemVerilog
Help improve and refine verification process, methodology, and metrics
UVM expertise on complex SoC projects from test bench development to verification closure

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