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Cadence

Our team is looking to hire a candidate who:
(1) Understands ASIC Design implementation process and steps
(2) Strong hands-on experience with Synthesis (Genus, RTL Compiler, Design Compiler)
(3) Exposure and experience with Test products (Modus, Encounter Test, Logic Vision,  DFT Compiler, etc)
(4) Experience with EDA tools in the IC digital implementation & signoff flows (STA tools)
(5) Strong STA and SDC debugging abilities are required.
(6) Low power analysis, Clock design/analysis, and hands-on 16/14nm experience a plus.
(7) Ability to understand and write RTL (System Verilog, Verilog, VHDL)

 

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