Should be a strong team player, excellent communicator as the role involves daily technical interaction with local, US counter parts. He/She will be part of SNPS DDR/HBM/UCIe/Die-to-Die IP implementation team and responsible for the implementation and integration of world class PHYs at the cutting-edge technology nodes. Timing closure above ~2GHz, mixed signal had macro IP integration, Building the efficient clock trees with very tight skew balancing are some of the challenges as part of day-to-day job. Prior working knowledge in the DDR/HBM/UCIe timing closure, implementation would be an added advantage. Should be very hands-on and able to technically lead a team of 4-6 junior engineers towards successful completion of project on-time and with top quality.


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