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Cadence

The ideal candidate should have:

Understanding of ASIC Design implementation process and steps Strong hands-on experience with Synthesis (Genus, RTL Compiler or Design Compiler) Exposure and experience with Test products (Modus, Encounter Test, Logic Vision, ​ DFT Compiler etc) Ability to understand and write RTL (System Verilog, Verilog, VHDL) Strong hands-on experience running Logic and Low Power Equivalency tools, ability to debug and isolate issues to tool or flow Debug and resolve complicated PPA, Low Power implementation and TAT issues related to Synthesis flows Be able to provide actionable feedback to downstream P& flows as well as derive actionable items from P&R data to tune synthesis flow to improve metrics

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