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Cadence

Mandatory: — BS/MS Engineering or Computer Sciences with 10+ years of VLSI circuit design/support experience — Rich experience in designing / leading implement ion of complex ARM cores with stretch PPA goals — Proven track record in handling high pressure competitive benchmark situations with C-level visibility — Expertise in problem-solving and inter-group coordination skills — Hands on knowledge of writing complex TCL scripts (EDI and ETS ) to workaround issues and get desirable results — Hands-on knowledge / skill set in Place & route technologies with emphasis in timing closure on high-speed cores

and more…

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