What opportunity is offered?

Candidates will find an opportunity in the Digital Synthesis, Place and Route and Signoff Analysis Application Engineering group.

As an intern, you will gain exposure with high-performance and low-power block implementation and signoff flows from RTL to GDSII. The intern will have the opportunity to participate in a three month program consisting of training and application of engineering software solutions for physical synthesis of Verilog, place and route flows and signoff timing analysis. The intern will also have an opportunity to interact and learn from Senior Application Engineers in pre-sale and post-sale roles.

How long is this Internship?
Duration of this Internship is three [3] months.

For more info, hit “Apply for job”