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Cadence

B.S degree in Electronics or equivalent with 4+ years of experience.
Good working knowledge of various verification concepts such as Verification architecture, coverage, checkers, test plan etc.
Strong in building Verification environments based on UVM, System Verilog and C.
Should have participated in building IP/full chip verification environments, verification planning and closure process.
Verifying the C/C++ based VIPs for proper functionality and system scenarios (including erroneous conditions).
Developing test suite and compliance test suite for 100% functional coverage for a given specification.
Outstanding all-round communication skills and ability to work collaboratively with multi-site and diverse team.
Interacting with internal and external customers and resolving issues in a timely manner.

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