Bachelors in Engineering with 2+years of experience or Master’s with 1+ years of experience.

Exposure to  analog circuit concepts/topologies.
Experience in mixed signal verification fundamentals, behavioral modelling, verification environment planning & development is a must.
Prior mixed signal verification experience in some of the serial bus protocol IP’s (PHY: USB/PCIE/SATA/Ethernet/DPHY/MPHY)
Experience in modelling such as real number modelling using Verilog-AMS/SV.
Basic experience in functional verification.
Should be process oriented and have a passion for scripting/automation
Good soft skills and experience of working collaboratively in cross site environment.

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