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Cadence

PHY design for memory interface IP development for DDR, LPDDR, GDDR, HBM product lines with a focus on analog design, top level phy planning, timing/jitter
Design of high speed custom logic for serialization, FIFOs, timing, clocking structures, data paths
Knowledge of analog building blocks such as drivers, receivers, interpolators, delay cells, DLL, PLL, clock trees, reference blocks.
Understanding of timing and jitter budgets

and more…

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