Functional Verification Engineer for DDR Memory Controller and Phy IP development team.
Position is based in Bangalore.
The role would include functional verification of the DDR Memory Controller and Phy IP solution of Cadence.
The work involved will be working with the existing functional verification environment, addition of new features into the verification environment, ensuring various customer configurations are clean as part of verification regressions, supporting customers in case of any issues with using the verification environment, and functional and code coverage.
The engineer would be responsible to ensure that the design is in line with the technical and quality requirements set for the team – particularly with respect to functional and code coverage.

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