Good Logical reasoning , Some knowledge of Verilog [ data types , block/non blocking , arrays , verilog timescale events]  ,  system verilog [ New data types , packages , struct , testbench interface & components] .
Basics of Design Verification flow, metrics (Functional Coverage, Code coverage, Assertion development/closure) and debug skills knowhow.
Mixed Signal verification experience from project work (if any)and /or knowledge of Cadence digital/analog verification tool is an added advantage.
Basic concepts of SerDes IP is preferred.
Hardworking, Committed and willingness to learn.

For more details, hit “Apply for job”