Position Description:

RTL Design Engineer for PCIe IP development team.
Position is based in Bangalore.
The role would include design and support of the RTL of the PCIe Gen3/4/5 IP solution of Cadence.
The work involved will be working with the existing RTL, addition of new features into the RTL, ensuring various customer configurations are clean as part of verification regressions, supporting customers, ensuring design is clean for LINT and CDC design guidelines.

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