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Strong background in mixed signal verification fundamentals,  verification environment planning & development is a must.
Clear concept of Basic Analog Circuits and Network theory
Behavioral modelling both for analog and digital.
Strong expertise in real number modelling using Verilog-AMS/SV.
Prior mixed signal verification experience in some of the serial bus protocol IP’s (PHY: USB /PCIE/DDR/DPHY/MPHY/Power Mangement)
Experience in functional verification is an added plus.
Experience in SV assertions development
Should be process oriented and have a passion for scripting/automation
Good soft skills and experience of working collaboratively in cross site environment.

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