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Cadence

Job Requirements:

* Strong expertise in Verilog, HVL( SV / Specman e) with UVM/OVM/eRM methodology
* Experience in functional coverage/code coverage/assertions development and closure.

* Experience in test plan creation.

* Exposure to PCIe and LPDDR verification.

 

Additional Job Description

* Strong debug skills
* Should be process oriented and have a passion for scripting/automation
* Should be a good team player