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Cadence

Knowledge of RTL coding and behavioural modelling in Verilog.

Experience in scan-based testing, stuck-at and transition fault modelling, ATPG test vector generation, and verification.

Knowledge of how to architect the structural testing of digital modules containing multiple high-speed internal clock domains, and their subsequent integration into SoCs.

Experience in fault coverage reporting and analysis.

Knowledge of industry-standard Design for Test tools, e.g. Cadence Genus and Modus.

Working knowledge of some or all of the following test standards and formats: IEEE 1149.1, BSDL and boundary-scan; CTL scan abstract files; IEEE 1687 (IJTAG) and associated ICL/PDL files.

Knowledge of TCL and Perl scripting languages.

Experience testing Analog and Mixed Signal designs is considered beneficial.

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