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Cadence

•             Cadence Synthesis (Exposure to Logic Synthesis) & Place and Route tool knowledge (Physical Synthesis, PnR, CTS, Static Timing Analysis) and experience

•             Broad knowledge and experience in the physical design process of modern SOCs (16/7nm or below) on actual tapeouts

•             Perform methodology assessments, improve existing design methodologies, and develop new ones that leverage Cadence technology and services.

•             Must have excellent debugging skills and an ability to prioritize critical issues from trivial ones.

•             Scripting experience with moderate/advanced TCL scripting skills is a must

•             Experience with the following :

design constraints(SDC) & ability to debug issues

Floor planning techniques for large blocks/top level designs containing memory and IP

Advanced Clock tree implementation

Static timing analysis, Power Analysis (Static, Dynamic, Leakage)

Timing optimization, in logical and physical mode

Low power implementation with knowledge of UPF is preferred

•             Possess a self-starter mindset with an established track record of complex problem solving in SOC physical design.

•             Excellent communication skills and be adept at working with both customer engineers/mgmt. as well as Cadence team members

•             Creates and presents internal and customer collateral including presentations, demos and workshops Provides guidance and mentoring to less experienced staff members

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