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Cadence

Position Description:

To develop & integrate foundry rule decks & technology files to support PDKs by using foundry provided process design kits as a starting point.
PDK QA, verification and release methodology for decks and specialized setups including track patterns to aid in layout.
Responsible for defining test vector and test structures/vehicle creation for PDK-QA and  implementing automated testing methodologies.
Responsible for rule deck development – to implement process design rules into physical verification rules decks and QC for the rule decks.
Pcell creation and enhancements to pcell parameters, device call backs.
Spectre model QA and usability enhancements.
Responsible for physical verification methodology, including development, qualification, automation, and support – To develop scripts to automate LVS, DRC, RM,IR and Parasitic Extraction flows. And to support layout teams in verification flow issues.
Developing scripts to port design databases- device to device, device parameters, layout layers and via mapping.
Responsible for interfacing with the design teams and foundry team to develop and verify our PDKs.
General tool usage support – real-time support of all tools, creating bug workarounds and filing CCRs with R&D

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