Cadence

Hand-on work experience of more than 10 + years in ASIC/IP/Subsystem/SOC/PHY level Verification primarily in protocols PCIe / NVMe / USB /SATA
Extensive experience in developing Verification environment and methodologies using Verilog / System Verilog / UVM / OVM / “e” Specman based languages
Proficient in PCIe PHY based protocol checkers / assertions using Verilog / SVA
Knowledgeable in integrating Serial-link VIPs, Verilog Real modelling of analog behavior and debug in various Industry Simulation tools
Hands on in regression setup, Coverage / Metric analysis and Vplan are preferable.

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