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Cadence

We are looking for a senior, experienced R&D engineer to help develop Cadence’s industry-leading Virtual and Hybrid platforms. We are looking for candidates who have the following experience:

Well-known expertise in SystemC and TLM modelling languages
Proven expertise in different TLM methodology and modelling abstractions
Deep expertise in C++, data structures, and algorithms
Extensive experience in developing complex Virtual Platforms
Extensive experience in developing complex TLM Models
Thorough knowledge and understanding of C++ build infrastructure
Extensive experience with debugging, tuning and bringing up pre silicon embedded software on virtual platform
Familiar to ARM Fast models. Prior experience in wrapping and integrating ARM FM into a virtual platform is a plus.
Proficient in using one or more scripting languages like Perl, Python, TCL
Experience in developing on Linux with GCC is a must
Knowledge of HDL (Verilog, VHDL), and/or verification languages (SV, e) is desirable
Knowledge of system bus protocols (e.g. AXI, ACE, OCP etc.) as well as common system interfaces like Ethernet, PCI Express, USB, HDMI etc is desirable.
Knowledge and hands-on experience in use of an hardware emulation system and/or a FPGA based prototyping system is a plus

For more & updated details, hit “Apply for job”