• Cary

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The position is for a Sr Principal Engineer specifically focused on the signal processing and logic design aspects of high-speed serial transceivers.

 

Responsibilities include:

Architecture and design of adaptation and calibration logic used in mixed-signal serial transceivers
Interfacing with analog design teams and driving specifications for analog and digital functional blocks
Verification of mixed-signal subsystems using System Verilog or equivalent
Review of RTL code written by various teams
Development of methodologies for code reuse and automatic code generation for functions over multiple projects
Interfacing with physical design (PD)

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