Website
Cadence

Cadence is looking for a Lead Design Engineer for Cadence DDR IO team. This person will work on design, verification of high speed transceiver blocks and be responsible for mentoring junior engineers.

Responsibilities will include, but are not limited to the following:

Analog/ Mixed Signal design engineer for Cadence DDR IO team
Position is based in Cary, North Carolina
Role would involve working on design, verification of high speed transceiver blocks
Role would involve mentoring junior engineers
Be part of a high-performing world-wide team responsible for delivering memory interface IO libraries to Tier1 OEM/ Semiconductor companies

For more details, hit “Apply for job”