Cadence is looking for a Analog/ Mixed Signal design engineer for Cadence DDR IO team. This person will work on design, verification of high speed transceiver blocks and be responsible for mentoring junior engineers.

Responsibilities will include, but are not limited to the following:

Communicate status, document results, and present design reviews to peers, customers, and senior staff
Working in leading edge sub 10nm design nodes
Be part of a high-performing world-wide team responsible for delivering memory interface IO libraries
Deliver high-quality IP to Tier1 OEMs/ semiconductor companies
Be part of IPG, the fastest growing business unit in Cadenc
This position is based in our Cary, North Carolina office

For more details, hit “Apply for job”